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I/O Block
Block
Mask
Description
This block gives access to all I/O modules configuration.
It is used with the Hardware Configuration block to determine all the interface modules available according to the requested signal type (analog or digital) and direction (input or output).
Implementation of the external connections is also available to enable offline simulation of the complete system, including external hardware setup. Note that the block input and output ports, as well as the parameters, depend upon the selected interface board.
Mask Parameters
| Type | Type of signal to be interfaced (either analog or digital). |
|---|---|
| Direction | The direction of the signal to be interfaced (either input or output). |
| Interface | Lists all available interfaces available according to the selected Type and Direction parameters and the configuration of the ‘HardConfig’ block. The user chooses the appropriate interface to manage the specific signal. |
| Characteristics | This parameter is not editable. It shows the interface board characteristics for easy identification of the board that corresponds to the selected interface location. |
| Show external signal port(s) | This checkbox is used to add input or output ports to the block that represent the external world, from the active control card point of view. These ports can be used to connect the signals to a model of the external device connected to the signal conditioning modules. This feature can be very useful for offline simulation of the FPGA model. |
Additional Parameters for Analog Input Interfaces
| Multiplex input/output signals | This checkbox can be used to concatenate multiple inputs or output signals on the same Simulink net. This may help the user to build cleaner schematics. If this option is selected, channels are multiplexed two by two, with a valid bit added. For example, the UFix33_0 format may be used for two analog output channels, the 16 LSBs being the first channel (in a format equivalent to the UFix16_10 numeric format), the next 16 bits being the second channel (also in a format equivalent to the UFix16_10 numeric format), and the MSB being the Valid bit. This format is useful for an easy connection to a DataIN or DataOUT block. |
|---|---|
| Note: The external analog signals for offline simulations are available on a channel-by-channel basis only. | |
| Number of channels | This parameter is used to select the number of channels to appear on the block icon. This option is not available when the Multiplex input/output signal option is selected. In this case, the channel number is set to the maximal value allowed by the selected interface board |
Additional Parameters for Analog Output Interfaces
| Maximum number of channels | This parameter can be used to specify that the Analog Output interface is used in high-speed mode. This is done at the cost of halving the maximum number of channels available in the interface. |
|---|---|
| Multiplex input/output signals | This checkbox can be used to concatenate multiple inputs or output signals on the same Simulink net. This may help the user to build cleaner schematics. If this option is selected, channels are multiplexed two by two, with a valid bit added. For example, the UFix33_0 format may be used for two analog output channels, the 16 LSBs being the first channel (in a format equivalent to the UFix16_11 numeric format), the next 16 bits being the second channel (also in a format equivalent to the UFix16_11 numeric format), and the MSB being the Valid bit. This format is useful for an easy connection to a DataIN or DataOUT block. This option is not available in high-speed mode. |
| Note: The external analog signals for offline simulations are available in a channel-by-channel basis only. | |
| Number of channels | This parameter is used to select the number of channels to appear on the block icon. This option is not available when the Multiplex input/output signal option is selected. In this case, the channel number is set to the maximal value allowed by the selected interface board |
Additional Parameters for Standard Digital Input Interfaces
| Multiplex input/output signals | This checkbox can be used to concatenate multiple inputs or output signals on the same Simulink net. This may help the user to build cleaner schematics. If this option is selected, the interface signal must be a multiple-bit fixed-point format (e.g.: UFix16_0 may be used for a 16-bit multiplexed digital signal) |
|---|---|
| Note: The multiplexed signals are always in an unsigned fixed-point format with the binary point at position 0 (i.e. a positive integer format). Also, note that the external digital signals provided for offline simulation correspond to the multiple-bit fixed-point number interfaced by this block | |
| Number of channels | This parameter is used to select the number of channels to appear on the block icon. This option is not available when the Multiplex input/output signal option is selected. In this case, the channel number is set to the maximal value allowed by the selected interface board. |
| Enable Digital Input Oversampling | This checkbox is enabling the oversampling of the input signals. The oversampling feature will sample the digital inputs at 4x the Oversampling clock. Then it will sum the samples. Example using https://wavedrom.com/editor.html. {signal: [
{name: 'Model main clock (200 MHz)', wave: '0hlhlhlhlhlhlh'},
{name: 'din channel', wave: '0.1...01....0.'},
{name: 'Oversampling clock (400 MHz)', wave: 'p.............'},
{name: 'Accumulated_Inputs [4]', wave: 'x0.1...01...0.'},
{name: 'Accumulated_Inputs [3:0]', wave: 'x3455556455563', data:["0x0","0x3","0x4","0x4","0x4","0x4","0x1","0x3","0x4","0x4","0x4","0x1","0x0"]}
]}
Accumulated_Inputs is sampled at the oversampling clock. Warning: placing a register will down sample the signal to the FPGA's clock frequency and data will be loss. When used with the eHS Gen5, it must be connected directly to a Gate input of the eHS core without any logic or delay on the line. The oversampling clock can be set and configured from the Synthesis manager block. |
Additional Parameters for Standard Digital Output Interfaces
| Multiplex input/output signals | This checkbox can be used to concatenate multiple inputs or output signals on the same Simulink net. This may help the user to build cleaner schematics. If this option is selected, the interface signal must be a multiple-bit fixed-point format (e.g.: UFix16_0 may be used for a 16-bit multiplexed digital signal) |
|---|---|
| Note: The multiplexed signals are always in an unsigned fixed-point format with the binary point at position 0 (i.e. a positive integer format). Also, note that the external digital signals provided for offline simulation correspond to the multiple-bit fixed-point number interfaced by this block | |
| Number of channels | This parameter is used to select the number of channels to appear on the block icon. This option is not available when the Multiplex input/output signal option is selected. In this case, the channel number is set to the maximal value allowed by the selected interface board. |
Inputs
The block inputs depend upon the parameters chosen in the block mask, and particularly upon the interface board used for signal conditioning:
Analog Input Interface
| Convert | Convert the input signal. Connect this input to the ModelSync From for synchronization with an external master device or provide an asynchronous sync source. If an asynchronous source is used, it must generate a 10 ns pulse. The maximum period between two pulses is 2 µs (maximum conversion speed of a channel). |
|---|---|
| Ch{0-15}_external | These signals correspond to the external-world inputs of the analog-to-digital conversion module. They are used only for offline simulation and appear only if the Show external signal port(s) option is selected in the block mask. They can be in a floating-point format. |
Analog Output Interface
| Convert | Convert the input signal. Connect this input to the ModelSync From for synchronization with an external master device or provide an asynchronous sync source. If an asynchronous source is used, it must generate a 10 ns pulse. The maximum period between two pulses is 1 µs (maximum conversion speed of a channel). To have synchronization of all the channels at the output of the digital-to-analog conversion card, all data samples should be presented in sync with the Convert signal. |
|---|---|
| Ch{0-15} | These ports are the output signals to be sent to the digital-to-analog conversion module (if the Multiplex input/output signals option is not selected). These signals represent the voltage of the module outputs. Note that these inputs are converted automatically to a Fix16_11 numerical format. Signals outside the [-16, 15.9995] dynamic range will be wrapped into a number in the range. Signals with a resolution higher than 0.0005V will lose precision. |
| Ch{1-15}_Ch{0-14} | These ports are the multiplexed output signals to be sent to the digital-to-analog conversion module (if the Multiplex input/output signals option is selected). These signals represent the voltage of the module outputs and must be in the UFix33_0 format. The 16 LSBs correspond to the first channel (in a format equivalent to the Fix16_11 numerical format), the next 16 bits to the second channel (also in a format equivalent to the Fix16_11 numerical format), and the MSB to a Valid bit (this bit is unused for analog output interfaces). |
Digital Input Conditioning Interface
| Ch{0-15}_external | These signals correspond to the external-world inputs of the digital conditioning module (if the Multiplex input/output signals option is not selected). They are used only for offline simulation, and appear only if the Show external signal port(s) option is selected in the block mask. They can be in a floating-point format. |
|---|---|
| DInput_external | This signal corresponds to the external-world inputs of the digital conditioning module (if the Multiplex input/output signals option is selected). It is used only for offline simulation and appears only if the Show external signal port(s) option is selected in the block mask. It can be in a floating-point format. |
| LoadIn, LoadInSOF | These signals are used to download configuration parameters (e.g Voltage Threshold). They only appear when the conditioning module expects them. |
Digital Output Conditioning Interface
| Ch{0-31} | These ports are the output signals to be sent to the digital conditioning module (if the Multiplex input/output signals option is not selected). These signals must be 1-bit wide. |
|---|---|
| DOutput | This port corresponds to the output signals to be sent to the digital conditioning module (if the Multiplex input/output signals option is selected). It is a concatenation of the digital output channels. Missing bits are padded by zeros, if the signal connected to this port have fewer bits than the interface module capacity. |
Digital Pass-Through Interface
| Direction | This signal corresponds to the direction of the digital pass-though lines. Its width must be equal to the pass-through interface module capacity (missing bits are padded with zeros). Zeros correspond to an outbound direction while ones correspond to an inbound direction. |
|---|---|
| DOutput | This port corresponds to the output signals to be sent to the digital conditioning module. It is a concatenation of the digital output channels. Missing bits are padded by zeros if the signal connected to this port has fewer bits than the interface module capacity, and lines that correspond to inbound signals (as indicated by the signal connected to the Direction port) are unused. |
| DInput_external | This signal corresponds to the external-world inputs of the digital conditioning module (if the Multiplex input/output signals option is selected). It is used only for offline simulation, and appears only if the Show external signal port(s) option is selected in the block mask. It can be in a floating-point format. |
Outputs
The block outputs depend upon the parameters chosen in the block mask, and particularly upon the interface board used to conditionate the signals:
Analog Input Interface
| Ch{0-15} | These ports are the input signals received from the analog-to-digital conversion module (if the Multiplex input/output signals option is not selected). These signals represent the voltage of the module inputs. Note that these outputs are in the Fix16_10 numerical format, giving them a dynamic range of [-16, 15.9995] and a resolution of 0.0005V. |
|---|---|
| Ch{1-15}_Ch{0-14} | These ports are the multiplexed input signals received from the analog-to-digital conversion module (if the Multiplex input/output signals option is selected). These signals represent the voltage of the module inputs and are in the UFix33_0 format. The 16 LSBs correspond to the first channel (in a format equivalent to the Fix16_10 numeric format), the next 16 bits to the second channel (also in a format equivalent to the Fix16_10 numeric format), and the MSB to a Valid bit (active when the 32 LSBs are updated). |
Analog Output Interface
| Ch{0-15}_external | These signals correspond to the external-world outputs of the digital-to-analog conversion module. They are used only for offline simulation and appear only if the Show external signal port(s) option is selected in the block mask. They are in the double floating-point format. |
|---|
Digital Input Conditioning Interface
| Ch{0-31} | These ports are the input signals received from the digital conditioning module (if the Multiplex input/output signals option is not selected). They are 1-bit wide unsigned signals. |
|---|---|
| DInput | This port corresponds to the input signals received from the digital conditioning module (if the Multiplex input/output signals option is selected). It is is a concatenation of the digital input channels. The signal width is equal to the interface module capacity. |
| Oversampled_Inputs | This port is to access the channels' value that are oversampled. The format of the signal is UFix_128_0. Each channel's value consists of 4 bits that are the oversampled acquisition. |
| Accumulated_Inputs | This port is to access the sum of each channels' value that are oversampled. The format of the signal is UFix_160_0. Each channel's sum value consists of 5 bits that are the concatenated as follow:
|
Digital Output Conditioning Interface
| Ch{0-15}_external | These signals correspond to the external-world inputs of the digital conditioning module (if the Multiplex input/output signals option is not selected). They are used only for offline simulation and appear only if the Show external signal port(s) option is selected in the block mask. They are in the double floating-point format. |
|---|---|
| DOutput_external | This signal corresponds to the external-world outputs of the digital conditioning module (if the Multiplex input/output signals option is selected). It is used only for offline simulation and appears only if the Show external signal port(s) option is selected in the block mask. It is in the double floating-point format. |
Digital Passthrough Interface
| DInput | This port corresponds to the input signals received from the digital conditioning module. It is a concatenation of the digital input channels. Its width corresponds to the interface module capacity, and lines that correspond to outbound bound signals (as indicated by the signal connected to the Direction port) are equal to the corresponding line of the signal connected to the DInput port. |
|---|---|
| DOutput_external | This signal corresponds to the external-world outputs of the digital conditioning module. It is used only for offline simulation, and appears only if the Show external signal port(s) option is selected in the block mask. It is in the double floating-point format. |
Specific interfaces
OP5330
This analog output conditioning card has a configurable maximum conversion rate. When the higher rate is selected, not all the channels are active. It is not recommended to change the rate while a simulation is running.
The output "RateSelectStatus" is available for validation. Possible values are 0 and 1 to indicate respectively a configuration of 1 MSPS or 2 MSPS.
1 MSPS
The default rate of the DAC is 1 MSPS. Under that rate, all the channels are active.
2 MSPS
When using the DAC of the OP5330 at 2 MSPS, only the following channels will be updated: 0, 1, 4, 5, 8, 9, 12, 13. The remaining channels will latch on their respectful last value.
There are different ways to use the rate of 2 MSPS.
Applying a rate of 2 MSPS without an input port
To be able to select the rate from the software (e.g. RT-LAB), the option of providing an input port for the specification of the sample rate must be set to "off". For the application under the software, please refer to its documentation.
OP5330 block without an input port for the configuration rate:
Applying a rate of 2 MSPS through an input port
Setting the option of providing an input port for the specification of the sample rate to "on" is mandatory for this way.
The designer of the RT-XSG model can then choose how the specification of the rate will be provided. It could be from the following ways, with the value "0" representing 1 MSPS and value "1" for 2 MSPS:
- Custom logic
- A constant
- A LoadIn port
OP5330 block with an input port for the configuration rate:
OP48H20 DAC
Similar to the OP5330, except it has 24 total channel instead of 16.
1 MSPS
The default rate of the DAC is 1 MSPS. Under that rate, all the channels are active.
2 MSPS
When using the DAC of the OP48H20 at 2 MSPS, only the following channels will be updated: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22. The remaining channels will latch on their respectful last value.
There are different ways to use the rate of 2 MSPS.
Applying a rate of 2 MSPS without an input port
To be able to select the rate from the software (e.g. RT-LAB), the option of providing an input port for the specification of the sample rate must be set to "off". For the application under the software, please refer to its documentation.
Applying a rate of 2 MSPS through an input port
Setting the option of providing an input port for the specification of the sample rate to "on" is mandatory for this way.
The designer of the RT-XSG model can then choose how the specification of the rate will be provided. It could be from the following ways, with the value "0" representing 1 MSPS and value "1" for 2 MSPS:
- Custom logic
- A constant
- A LoadIn port
OP48H20 block with an input port for the configuration rate:
OP48H30 DAC
Similar to the OP5330 and OP48H20, except it has 48 total channel instead of 16 or 24.
1 MSPS
The default rate of the DAC is 1 MSPS. Under that rate, all the channels are active.
2 MSPS
When using the DAC of the OP48H30 at 2 MSPS, only the following channels will be updated: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46. The remaining channels will latch on their respectful last value.
There are different ways to use the rate of 2 MSPS.
Applying a rate of 2 MSPS without an input port
To be able to select the rate from the software (e.g. RT-LAB), the option of providing an input port for the specification of the sample rate must be set to "off" :
If you want to be able to configure it runtime, you might want to use the RateSelectStatus output port to select the right convert rate :
For the application under the software, please refer to its documentation.
Applying a rate of 2 MSPS through an input port
Setting the option of providing an input port for the specification of the sample rate to "on" is mandatory for this way :
The designer of the RT-XSG model can then choose how the specification of the rate will be provided. It could be from the following ways, with the value "0" representing 1 MSPS and value "1" for 2 MSPS:
- Custom logic
- A constant
- A LoadIn port
OP48H30 block with an input port for the configuration rate:
Using this method will bypass the RT-LAB programming of the register.
OP5369, OP48H10 & OP48H30 DIO
This I/O conditioning card has programmable features that are implicit or user modifiable. The features are:
Direction IN or OUT programming per group of 8 channels for the OP5369 and OP48H10 and 16 channels for the OP48H30
Threshold High and Low Values programming Low and High threshold voltages (pertained to INPUT configured ports only)
The implicit values are the ones managed by the FPGA itself, and the user modifiable values are the ones managed by software or a combination software-FPGA.
Mainly there are 2 basic options in the user interface: 32 ports or 64 ports.
In the 32 ports, the IO block will show 32 ports for the real 32 channels of the board. The direction and threshold values are set by the RT-XSG designer through the GUI options.
There is no support for 16 IN and 16 OUT directions. To have these configuration, see 64 ports options.
In the 64 ports, the IO block will show 64 ports for covering the possibilities of programming the 32 real channels by group of 8 without re-generating a bitstream.
The option "Configuration control mode" has the "From application" option which consists to program the direction through the usage of the Selectable Digital IO application blocks interface connected to the OP5369 IO block. For other application, i.e. using not the Selectable DIO, more options will be defined or will be available on demand.
Note that the difference with the OP48H30 is that it instead has 64 channels. so basically, 32 ports mode and 64 ports model respectively become 64 and 128 ports mode, but the logic remains the same.
32 ports IN OUT OPTIONS
Implicit direction (no threshold programming).
32 ports IN OPTION
Implicit direction and threshold programming.
32 ports OUT OPTION
Implicit direction (no threshold programming).
64 ports
OP5369 and OP48H10
From application direction programming.
The selectable Digital Output are managed by the Load Data and Load SoF interface linking the software with the FPGA for programming management. The features of the OP5369 shall not be modified during the runtime of the simulation, (the Load interface is active during Load state of the simulation).
Detailed descriptions of the OP5369 optional programming modes
Under the 64 ports design, the Direction can be set by the selectable blocks: when the selectable DOUT is configured, the OP5369 will be configured as output for all the channels within the subsection.
Subsection 1 OUT enable affects channels 0 to 7.
Subsection 2 OUT enable affects channels 8 to 15.
Subsection 3 OUT enable affects channels 16 to 23.
Subsection 4 OUT enable affects channels 24 to 31.
Otherwise, if the INPUT direction is desired, because the OP5369 is programmed in INPUT direction by default, it will not be programmed in OUTPUT direction.
Subsequently, if the Selectable DO is not configured for the SubSection 1, the IO Block CH0-CH7 inputs will be the active channels for acquiring data from the external world of the simulator.
Same reasoning for SubSection 2 to 4 for the remaining channels.
Selectable DO subsection | IsConfigured value | Active Direction |
|---|---|---|
SubSection 1 OUT | 0 | CH0-CH7 Inputs activated |
SubSection 1 OUT | 1 | CH0-CH7 OUTPUTS activated |
SubSection 2 OUT | 0 | CH8-CH15 Inputs activated |
SubSection 2 OUT | 1 | CH8-CH15 OUTPUTS activated |
SubSection 3 OUT | 0 | CH16-CH23 Inputs activated |
SubSection 3 OUT | 1 | CH16-CH23 OUTPUTS activated |
SubSection 4 OUT | 0 | CH24-CH31 Inputs activated |
SubSection 4 OUT | 1 | CH24-CH31 OUTPUTS activated |
All subsections are covering 8 ports for setting the 8 real hardware channels. Every subsection is grouping 8 channels for the direction programming. All channels within a group have the same direction. But 2 different subsections of 8 channels could have different directions.
The threshold configuration is made internally by the FPGA itself. It is related to the Input direction only. There are 2 threshold values: one for the digital low logic (Vtl) and one for the digital high logic (Vth). If Vth = 2.0 V and Vtl = 0.8 V, then a voltage passing from 0 to 2.0 V and more will be a digital logic 1, and the voltage passing from 2.0 V to under 0.8 V will be a digital 0.
OP48H30
For the OP48H30, the logic is similar, except the banks are controllable by groups of 16 instead of 8, so instead of having 4 enable ports, we have only 2 :
Subsection 1-2 OUT enable affects channels 0 to 15.
Subsection 3-4 OUT enable affects channels 16 to 31.
The same rules as far as the direction programming apply, although the the connections are a bit different :
As you can see, only one port Enable configures the configuration for two 8 channel data ports, meaning you only have to connect one of them to the application bloc of your choice (here the SDO bloc).
Threshold values
OP5369
These are the default thresholds applied the digital channels when used in input mode. They are configurable by group of 8 and can then be overridden by software when running your model.
Low threshold means the voltage under which a previous digital HIGH value becomes LOW (VTL).
HIGH threshold means the voltage over which a previous digital LOW value becomes HIGH (VTH).
OP48H30
The same logic applies as for the OP5369, but again, the thresholds are programmable by groups of 16 instead of 8
Note : The threshold menu is also available in 32 ports mode, but only when setting the direction to IN.
Characteristics and Limitations
This block has no special characteristics.
| Direct Feedthrough | NO |
|---|---|
| Discrete sample time | NO |
| XHP support | N/A |
| Work offline | YES |
OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
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