How to interconnect mutiple eHS Cores

As previously explained, gated signals have a time resolution higher than the RT-LAB simulation step size. These signals are typically pulse-width modulated signals (PWM), and are generated by the FPGA firmware with a time resolution in the order of 10 nanoseconds. Hence, these signals can be sampled at the eHS computation rate. On the other hand, input signals generated by RT-LAB will, by default, be sampled with a sampling period equal to the RT-LAB simulation step size, which is in the order of 10-50 microseconds. A better resolution can be achieved either by generating the signals directly on the FPGA, by taking inputs from the external world via an analog input interface, or by interconnecting multiple eHS solvers.

By default, eHS sources are accessed through the eHS block and are sent from the CPU of the simulator.

As illustrated in Figure below, the source control signals of either eHS can come from RT-LAB, from the output of the other eHS solver, or from any other FPGA-based solver. The selection is made for each individual signal in the “Input Settings” tab by routing the control of a source by another eHS output.

Note that a diagram of the firmware is required to be sure of the solvers interconnection settings.

Interconnection pattern between the two eHS solvers with custom firmware.

Note: FPGA-based sinusoidal source or gating signal generators, as well as other solver interconnection patterns such as machines models, can be implemented with the help of the RT-XSG toolbox or with the help of the OPAL-RT development team.