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Selectable Digital Output - efs_cpuSelectableDO

Block


Table of Contents

Description

This block implements an 8-channel digital output subsection as either Static digital output, EventGenerator output or Pulse-Width Modulated output.


Mask Parameters

Controller Name:Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.

DataIn port number: Enter the number of the DataIn port to be controlled by this block, in the range [1:32].

LoadIn port number for Digital Output type selection: Enter the number of the LoadIn port used to communicate the Digital Output type selection for this block, in the range [1:32].

Digital Output type: Select the Digital Output type from the list. This type can either be "Static Digital Output", "Event Generator" or "Pulse-Width Modulated Output".

Other parameters will appear depending on the Digital Output type selection. More information on these parameters can be found in the block documentation of either digital output type.


Inputs

Inputs of this block are Digital-Output-type dependent. Refer to the block documentation of either digital output type for more information.


Outputs

Outputs of this block are Digital-Output-type dependent. Refer to the block documentation of either digital output type for more information.


Characteristics and limitations

The block documentation of either digital output type can be accessed here: Static Digital Output, Event Generator, Pulse-Width Modulated Output,

Direct FeedthroughNO
Discrete sample timeYES
XHP supportYES
Work offlineN/A


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