Description

This model illustrates the use of the stubline to couple a CPU model to eHS through transformer inductance. In the same model, three circuit, are being simulated. One with the stubline between the CPU and eHS, one with a stubline only on CPU, and one without decoupling. As it can observed, all measurements are superimposed.

In S-Function workflow, example models support any chassis. You can contextualize your example model by selecting the chassis in the Chassis selection block.

SCHEMATIC EDITOR S-function OP4512 OP4610 OP5607 OP5707

Table of Contents

Requirements

The RT-LAB, Schematic Editor/Unified Database and eFPGASIM toolboxes must be installed on the host and target computers in order to run this example model properly. Please refer to the product documentation for details on version compatibility.

Setup and Connections

This model does not require any IOs, as it is more a demonstrator of the expected results.

It is possible to execute this simulation in different chassis. The "Simulator Selection" block in "stublineTransformer" root allows the user to select the appropriate target and automatically change the configuration and firmware.

Procedure

RT-LAB model with eHS interface

Run this demo : efsOpenExample('StublineXfo_SE_rtlab');

The following procedure will help the user understand the functionality and linking between eFPGASIM, RT-LAB and Schematic Editor. A Hardware-in-the-loop based RT-LAB model, "stublineTransformer", is provided to illustrate this example.

Click on "Run this demo" at the top of this section. The RT-LAB model will open automatically.
The RT-LAB model consists of a master subsystem (i.e. "sm_computation") and a console subsystem (i.e. "sc_user_interface").
- The master subsystem has power network interface ("eHS_SE_SFunction_Drivers")
- There is a model using stubline all in CPU
- There is a model without decoupling

The console subsystem is used to control the switch to vary the load on the DC side. Results from the three different implementations can be observed as well.

The "eHS_SE_SFunction_Drivers" solver solves the power network built using schematic editor software during the real time simulation. The circuit built in schematic editor can be edited or viewed by choosing the edit option available in the solver block. The stubline connection is done through the half-line block. Similar block can be found in sm_computation, note that the same parameters must be entered in both CPU and eHS model.

Stubline configuration

Stubline can be used as either a series-inductor or a shunt-capacitor where its value is given either in henry or farad. The other parameter to select is the decoupling latency which is the time it takes for a signal measured in eHS be sent to the CPU. When adding an inductive stubline, parasitic capacitance are also added. In the case of a capacitive snubber, parasitic inductor are added.

In this example, Decoupling Latency is equal to 3 time the CPU sampling time, or 30µs

eHS FPGA-based Power Electronics Toolbox

v2.18 Stubline Transformer - S-Function - eHS Gen4