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The OP8320-4 was specifically designed to terminate OPAL-RT TTL digital I/O boards when connections between simulator and units under test are longer than 1.5m (5 feet).

The board provides open sockets, on channel 0, on which you can test various terminations. Once those terminations are confirmed, you can apply the desired termination by soldering components to the appropriate channel.

OP8320-4 Board Interface

Current Regulating Diode Specifications: Use through-hole 0.3mm axial diodes and solder using SMT 1206

Typical Installation

OP8320 Flow Diagram

Termination Outputs

When connecting OPAL-RT digital inputs or outputs TTL/CMOS boards with third-party devices (or user ECUs), there are certain steps to ensure good signal integrity over transmission lines with a matching scheme to absorb any reflections that may be generated by the source, the driver or load, and the receiver.

The standard termination configuration components are shown in the schematic below.  Note that circuits all have diodes installed by default.

With this circuit, the OP8320-4 offers five different options of termination circuit, described below:


R2. Default configuration 10Ω


R3 & C1=0Ω
TheveninR1 & R3
ACR3 & C1


30V rating

Series Termination

Series termination consists of a resistor in series with the driving device output. Users have two alternatives depending on where the resistor is located:

  • If the resistor is not located on the device, the value of the resistor should be R = ZO – ZD (ZD is the driver output impedance). Place the resistor as close to the driver as possible.
  • If the resistor is integrated on the device and part of the chip, its value is usually 25Ω ≤ R ≤ 33 Ω  (useful for point-to-point driving).

Series Termination Circuit Diagram

Parallel Termination

It consists of a single resistor tied to GND. The ideal value of the resistor is R = ZO, and the best placement for it is as close to the receiver as possible. A heavy increase in power occurs, but no further delay is present. There is a relatively low DC noise margin in this configuration.

Parallel Termination Circuit Diagram

Thevenin Termination

It involves two split resistors: one resistor (R1) is tied to VCC and the other (R2) is tied to GND. The ideal value of the resistors is R1 = R2 = 2ZO; RT = (R1 x R2)/(R1 + R2), and the best placement for the resistors is as close to the receiver as possible.

This results in a heavy increase in power, with no delay, and is primarily used in backplane designs where proper drive currents must be maintained.

Thevenin Termination Circuit Diagram

AC Termination

It has a capacitor in series with a resistor, both of which are running parallel to GND. The ideal value of the resistor is R = ZO, and the value of the capacitor should be 60pF < C < 330 pF. 

They should both be placed as close to the receiver as possible.

This consumes the most power as the frequency increases, but no additional delay is experienced.

Note: This termination technique can be optimized for only one signal frequency.

AC Termination Circuit Diagram

Diode Termination

It consists of a diode to GND that should be located as close to the receiver as possible. There is no increase in power, no delay, and this configuration is useful for standard backplane terminations.

NOTE: This is the most attractive of all techniques since there is no power increase and no delay.

Diode Termination Circuit Diagram

30V diodes are always installed on all versions of the OP8320 board.

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | | +1 514-935-2323