The OP4810-IO and OP4815-IO are I/O expansion units that include top-of-the-lineAMD Versal™ Prime adaptative SoC line of compute engines (FPGA). They are designed to add powerful FPGA compute capabilities and plenty of additional and fast I/Os to OPAL-RT’s real-time HIL simulators. They are compatible with the OPAL-RT simulators:
They also include12 SFP ports in the front, and in the back, 4 RS-422 DB9 connectors offering 6 Rx and 6Tx (default proposed configuration that can be replaced by optical fiber connectors).
The OP4810-IO/OP4815-IO FPGA Processor and I/O Expansion Units are compatible with RT-LAB and HYPERSIM software andeHS, MMC, RT-XSG toolboxes. Used with OPAL-RT’s RT-LAB and eHS, FPGA based power electronics toolbox, the OP4810-IO and OP4815-IO will smoothly run all real-time power electronic models.
The OP4810-IO and OP4815-IO are designed to be used either as a desktop, shelf top, or mounted in a standard 19″ rack.
The OP4810-IO and OP4815-IO are exactly the same, except for their AMD Versal™ Prime compute engines (FPGA).
The front of the chassis provides access to the SFP ports, the fiber-optic synchronization connectors and the RJ45 Ethernet ports. The back of the chassis provides access to the DB37 and DB9 I/O connectors,target power cable, and main power switch.
The AMD Versal ™ Prime Adaptative SoC (FPGA) execute models designed with OPAL-RT software and toolboxes, manage the I/O lines and execute embedded FPGA-based simulations.
It exchanges data with the real-time simulations running on the remote target computer CPUs via the PCIe link.
12 SFP ports are available for high-speed communication with other OPAL-RT FPGA-based systems or with external devices. The standard communication protocols available with the OP4810-IO/OP4815-IO are based on the Aurora protocol (2 to 5 Gbps). Other protocols, such as the Gigabit Ethernet, can also be implemented.
4 SFP ports numbered CH00 through CH03 are reserved to expand an OPAL-RT’s simulator I/O capability using OPAL-RT’s Multi-System Expansion link (MuSE). They are identified MuSE numbered CH00 through CH03 on the front plate (photo below). MuSE link is compatible with OPAL-RT boards I/O management architecture. NOTE: MuSE will not be supported with the release of RT-LAB and HYPERSIM (version 2024.2) at time of first product delivery. Expect Q1-2025 for MuSE support in RT-LAB and HYPERSIM.
The 8 SFP ports numbered CH04 through CH11 not used for MuSE are compatible with the legacy generic Aurora link.