4.8 Configuring the Local Controller

Local Controller File Path: <Public Documents>\National Instruments\<NI VeriStand 20XX>\Examples\OPAL-RT\Power Electronics Add-On\SCIM Constant Local Control\Local Controller

A simple closed-loop SPWM frequency and modulation index controller model was developed for this example and compiled into a .so file for execution on Linux RT targets.  The controller model is configured to run on the Real Time CPU and will be executed by the VeriStand Engine.  Data is routed from the CPU simulation (local controller) to the FPGA simulation using the VeriStand System Configuration Mappings.

Open

Exploring the Local Controller

• In the Configuration Tree, expand Controller >> Simulation Models >> Models. Click ClosedLoopVoltPerHertzController to view the model file information.

• In the Configuration Tree, expand ClosedLoopVoltPerHertzController >> Inports and confirm that all inports have been configured as shown in the table below.

• Click Save.

Inport	Default Value

Inport	Default Value
Dclink	0
DesiredSpeedRPM	0
ModIndexLookup	Open
Poles	3
RampRate	50
SpeedRPM_I	0.001
SpeedRPM_P	0.01
SpeedRPMProcess	0

 

 

Exploring the Mappings to and from the Local Controller

The VeriStand System Configuration Mappings are used to route signals between the local controller and the other model components simulated on the FPGA. 

• Close the VeriStand System Explorer window, to return to the VeriStand Editor

• Open the System Definition file (.nivssdf)

• Confirm that the signals are mapped together as shown in the image below.