Gates Section

Gates Configuration Page

In the System Explorer window configuration tree, expand the Power Electronics Add-On (OPAL-RT Circuit) custom device and select Circuit >> Gates to display this page. After a model is successfully loaded in the Circuit Section, this page is added to the configuration tree and populated with a named list of the Gates components found in the circuit model. An incoming digital signal must be mapped to each switch to control its state as it is simulated in the eHS solver.

For each switch, the following information and mapping options are available at edit-time.

Switches Settings
Name	Displays the name of the Gate. Refer to the Switches documentation for all supported gate components.
Source	Filters the list of available elements to be mapped to the Gate. The available options are defined by the selected Hardware Configuration, however it is typical to see the following options by default:
	CPU (VeriStand)	VeriStand custom device channels on the CPU. If this Group is selected, the Element dropdown is populated with a single option displaying the name of the custom device channel whose value is mapped.
	PWMs	PWM outputs of the PWM Generators Section. In the Element dropdown, select the index of the PWM Generator whose output signal to map.
Element	The name or index of the signal to be mapped to the switch. The options available in this dropdown depend on the selected Source.
Polarity	The polarity of the switch component. Active High switches are open when LOW is applied to the gate and closed when HIGH is applied to the gate. Active Low switches are closed when LOW is applied to the gate and open when HIGH is applied to the gate

Gates Section Channels

After a model has been loaded in the Circuit Section, the Gates section of the Configuration Tree is populated with a list of channels corresponding to each gate component found in the circuit model that has the Comes from VeriStand Channel option selected. Switches connected to a Digital Input will not appear as a VeriStand channel in the system definition tree.

If a gate is mapped to the CPU (VeriStand) Group described in the Gates Configuration Page section, then the value of its corresponding channel defines the state of the gate during the simulation. If the CPU (VeriStand) Group is not used, then the value of the channel does not affect the circuit simulation.

Gates Description

Gates accept gating control signals. They are controlled with digital signals (i.e. HIGH, LOW signals) which can come from custom device channels, digital inputs, signal generators, and more. Switches modeled in eHS are characterized by their Switch Conductance (Gs). Refer to the Switches documentation for all supported gate components.