PXIe-7891 (KU60) - eHS - Gen5 - CONF 1

Specifications

IO Capabilities

This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.

Quantity	FPGA Board

Quantity	FPGA Board
1	PXIe-7891

The PXIe-7891R supports the following features:

IO Type	Details

IO Type

Details

Analog Input

18 CH, 2MS/s, 16-bit, +/- 20V Input Signal Range, Differential

Tunable Gain, Offset, and Min/Max Saturation

Analog Output

64 CH Total: 32 CH, 4MS/s, 16-bit & 32 CH, 2MS/s, 16-bit, +/- 10V Input Signal Range

User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.

Measurements

Digital Input

0-64 CH, 10MHz, 3.3V or 5.0V TTL

Refer to 7891 IO Pinout [PXIe-7891 (KU60) - eHS - Gen5 - CONF 1] to see the IO assignment.

Modeling Capabilities

This configuration includes a pre-compiled firmware/bitfile which contains the following features:

Features	Low Latency Support

Features	Low Latency Support
1x eHSx128 GEN5 Solver	⚪
32x Sinewave Generators	⚪
16x PWM Generators	⚫
64x Analog Outputs	⚪
16x Analog Inputs	⚪
0-64x Digital Inputs	⚪
32x Waveform Acquisition Channels	⚪
Telemetry Channels	⚪

⚫ = Supported ⚪ = Not Supported

In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments.