Documentation Home Page ◇ Power Electronics Add-On for NI VeriStand - OPAL-RT Circuit Home Page
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.
Circuit Section
Page Content
Circuit Configuration Page
In the System Explorer window configuration tree, expand the Power Electronics Add-On custom device and select a Circuit section to display this page. Use this page to add an electrical model to the VeriStand System Definition. When the VeriStand project is deployed, the circuit model is simulated on the FPGA through the eHS Solver.
This page includes the following components, configurable at edit-time only:
Model | |
Name | Specifies the name of the circuit model. |
Description | Specifies a description for the circuit model. |
Target Name | Specified the Name of the FPGA target onto which the circuit model will be deployed and simulate. |
Circuit File Path | Specifies the path to the circuit model file (.ehs3) on disk. When a file path is added, the circuit file is parsed and VeriStand channels are created corresponding to the Source, Gate, and Measurement components defined in the circuit model. Component configuration settings are set to their default states. Other components such as PWM Generators, Waveforms, etc may also be added to the system definition tree based on features available in the firmware. |
Create New Circuit | Prompts the selection of a file path to create a new circuit model on disk. The circuit model is also opened in the Schematic Editor for editing. |
Edit | Opens in the circuit model at the specified Circuit File Path in the Schematic Editor for editing. |
Reload | Parses the currently specified circuit model and updates the VeriStand channels. Components whose names have not changed retain their previously configured settings, while new or modified components are reset to the default state. Components that are no longer part of the model are removed. |
Clear | Removes the currently loaded circuit model. When a circuit model is cleared, the corresponding Source, Gate, and Measurement sections (and any other sections below the Circuit page) are deleted from the Configuration Tree and all related mapping configuration settings are removed. |
Last Updated | Specifies the date and time when the currently specified circuit model was updated last |
Additional Information | |
Applied Timestep (s) | Specifies the execution timestep of the circuit model. |
Minimum Timestep (s) | Displays the smallest timestep at which the eHS Solver can simulate the circuit model. |
Maximum Timestep (s) | Displays the largest timestep at which the eHS Solver can simulate the circuit model. |
Circuit Section Channels
This section includes the following custom device channels. The value of an input channel can be modified dynamically at execution time.
Channel Name | Type | Default Value | Description |
---|---|---|---|
Parameter Set | Input | 0 | Specifies the index of the parameter set to be simulated. Modify the value of this channel at run-time to switch between parameter sets. This channel is only available when Parameter Sets are configured in the circuit model. |
Reset | Input | 0 | This channel resets in the circuit simulation. Set this channel to one of the following values:
Circuits in Reset mode do not react to inputs, and their outputs should not be considered as valid. Please refer to the Reset Model Behavior section for more information. This channel is only available when Reset Pin in the Solver Setting of the circuit is enabled. |
Related Links
OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter