Xilinx System Generator Toolbox Integration

Starting with RT-LAB v8.3, the integration between the Xilinx System generator toolbox and RT-LAB requires the use of the new OPAL-RT RT-XSG. RT-XSG provides all files required for preparing Simulink models that can be built into FPGA bitstreams for the OPAL-RT products. RT-LAB only contains the files and drivers needed for interacting with these OPAL-RT boards during the real-time simulation. RT-LAB examples models for real-time simulations integrating OPAL-RT boards supported by RT-XSG can be found under the <RT-LAB_ROOT>\Examples\IO\OPAL-RT folder.

These examples are thus CPU models, i.e models that run on the CPU of the target machine to which the board is connected. The structure of these models is described in the following sections. The OP5130-XSG subdirectory, for example, contains one basic example model that performs data exchange with an OP5130 board programmed with a bitstream generated with RT-XSG.

The generated bitstream is provided with this example model and is loaded into the FPGA of the OP5130 at model load time. However, if the user wants to modify the logic implemented in this bitstream, he must use the RT-XSG product, edit the basic Simulink-XSG example model for this board provided in the RT-XSG folder, regenerate the bitstream, and then copy it to the RT-LAB example model folder.

Preparing CPU Models

It is assumed that the reader is familiar with the Xilinx System Generator as presented in Xilinx SysGen user guide. In the following, the discussion focuses on the use of the OPAL-RT OP5130 board, although the process of preparing models for other supported boards will be similar. When designing and XSG-based RT-LAB application, two Simulink models must be developed. The first one, hereafter called the FPGA model, contains the XSG and RT-XSG blocks required to build the bitstream to be downloaded in the FPGA-chip of the reconfigurable I/O card.

The second model, the CPU model, runs on the target node and must contain one interface block, the OpCtrlReconfigurableIO block, in order to manage communication between the CPU model and the reconfigurable I/O card. This block can be seen as a bridge between software and hardware.

It communicates and receives in real-time the data samples to and from the OP5130 reconfigurable IO card through the OPAL-RT SignalWire communication link. An example CPU model is presented in Figure 20. In this example, the OpCtrl ReconfigurableIO block is set up with 16 IN/OUT communication ports, thus allowing transfer of 16 32-bit values of data to and from the OP5130 card at each calculation step. The number of inports and outports of the OpCtrlReconfigurableIO block is configurable between 0 and 16. Note that the width of each inport and outport can also be increased up to 250 32-bit values if required by the application.

Example of a CPU model

In this particular example, the inports of the OpCtrlReconfigurableIO block placed in the CPU model are connected to signal generators that generate samples to be transmitted to the OP5130 at a rate of Ts=200us.

These signal generators create a saw, a sin and a square waveform. Notice that these signals pass through a subsystem named "double to uint32 convert" that converts the generators double type signals to the uint32 type.

This is the default type supported by the OpCtrl ReconfigurableIO on either its inputs or outputs. Besides doing signal conversion, the subsystem does signal scaling and concatenation. Scaling is necessary before the type conversion so that decimal values are not truncated. In this particular case, the waveform signals are routed to a DAC interface in the FPGA XSG model which expects the Xilinx Fix16_11 format. So a "Shift Arithmetic" block shifts the three waveform signals by 11 bits to the left (i.e multiply them by 2^11).

Conversion subsystem connected to the inports of the OpCtrlReconfigurableIO block.

Inside the three Concatenation subsystems you will find the type conversion blocks as well as the concatenation logic. Concatenation is necessary in this case because the waveform generators are connected to a DAC I/F with 16 bit channels.

Concatenation of 2 16-bit data values into one single value to be transmitted to the OP5130 Input port In1 takes care of the lower 16 bits and input port In2 of the upper part.

In this example, both ports are connected to the same source and come out of output port 2, sawout, of the "double to uint32 convert" which in turn is connected to the input port number 2 of the OpCtrl ReconfigurableIO block. This port corresponds to one entry port of the FPGA model, which, in this example, is directly connected to the OP5330 DAC interface block.

Each of the DAC input port of this block represents two 16 bit concatenated channels.

Signal concatenation as presented above is not mandatory and depends on the logic implemented in each FPGA model, but it is advantageous because it uses the available bandwidth more efficiently.

The outputs of the OpCtrlReconfigurableIO block are used to retrieve data from the OP5130 board at each calculation step. The samples are transmitted to the target node via the SignalWire link. Here again some transformation of the data may be needed. The figure below shows the type of transformation done in the "data reformatting from uint32 to double" subsystem to extract 16-bit ADC samples and convert them to the double type. Note that a shift arithmetic block is used to scale the information properly. Since ADC samples are in the Fix_16_10 format in the FPGA, a shift by 10 bit to the right is necessary in the target.

Conversion subsystem connected to the inports of the OpCtrlReconfigurableIO block.

Limitations

• As of RT-LAB v8.3, the only reconfigurable IO card supported is the OPAL-RT OP5130 card. RT-LAB support for new RT-XSG-supported boards such as Xilinx ML506 development board and OPAL-RT Spartan3-based module is under way and RT-LAB examples for these boards will be integrated in future releases.
• Communication between multiple OP5130 reconfigurable IO card is not yet possible. However, it is possible to place several OpCtrlReconfigurableIO blocks in the model in order to communicate with several OP5130 cards from the same CPU model. The ‘Search Strategy’ option of the OpCtrlReconfigurableIO block must then be used to differentiate between the OP5130 cards.
• Only 16 32 bit IN/OUT ports are provided by the DataIN/OUT blocks, and the maximum width of each of these outputs is 250 samples.