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OpSyncNI671x

Block

Mask

Description

This block enables hardware synchronization of the model where it is inserted. The block uses both timers of the NI671x card.

Counter 0 is used to output a pulse-train, the period of which is equal to the calculation step of the model.

Counter 1 reads the output signal of counter 0 and synchronizes the model on the rising edges of this signal.

The only connection required is thus between OUT0 and GATE1.

The output signal of counter0 can also be used to synchronize the acquisition of other I/O blocks, such as the OpNI6602 Event Generator block, or the OpNI6602Event Detector block.

Parameters

Bus TypeSpecify the type of the bus, PCI or PXI, of the target computer.
Board TypeSpecify the model of the card: NI6711 or NI6713.
PCI indexEnter the PCI index (see definition)of the card on the PCI (or PXI) bus.

Inputs

This block has no inputs.

Outputs

This block has no outputs.

Characteristics and Limitations

Connector Pin Assignments

As mentioned in the functional description above, the output pin of counter 0, OUT0, produces the reference signal. This signal must be connected to GATE1, the gate pin of counter 1.

The table below gives the connector pin assignments of the 68-pin I/O connector.


NI671x 68-pin connector

Pin Description Number Pin Description Number 
AOGND 34NC68
NC 33AOGND67
AOGND 32AOGND66
AOGND 31DAC7OUT65
DAC6OUT 30AOGND64
AOGND 29AOGND63
DAC5OUT 28NC62
AOGND 27AOGND61
AOGND 26DAC4OUT60
DAC3OUT 25AOGND59
AOGND 24AOGND58
AOGND 23DAC2OUT57
DAC0OUT 22AOGND56
DAC1OUT 21AOGND55
EXTREF 20AOGND54
DIO4 19DGND53
DGND 18DIO052
DIO1 17DIO551
DIO6 16DGND50
DGND 15DIO249
+5V 14DIO748
DGND 13DIO347
DGND 12NC46
PFI0 11EXTSTROBE45
PFI1 10DGND44
DGND 9PFI243
+5V 8PFI3/G1_SOURCE42
DGND 7PFI4/G1_GATE41
PFI5/UPDATE 6G1_OUT40
PFI6/WFTRIG 5DGND39
DGND 4PFI738
PFI9/G0_GATE 3PFI8/G0_SOURCE37
G0_OUT2DGND36
FREQ_OUT 1DGND25
Direct FeedthroughNo
Discrete sample timeNo
XHP supportYes
Work offlineNo

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