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Location

This example model can be found in the software under the category "How To" with the file name "FPGA_Scope.ecf".

Description

This example project is intended to demonstrate the use of the FPGA Scope on an OP4610XG simulator. The FPGA Scope feature is used to visualize high-speed signals internal to the OP4510 FPGA board with a sampling rate higher than the simulation step size. The project implements sine-wave generators and pulse-width modulators, which are sent to the analog and digital output interfaces of the simulator, respectively. These are intended to be looped back into the analog and digital input interfaces of the simulator.

In this demonstration, the FPGA Scope will be used to:

• Measure the latency and noise level of the analog output and input conversion interfaces;

• Visualize the enhancement in the precision of the FPGA-based pulse-width modulators compared to the simple Simulink-based modulators;

• Measure the latency in the digital output and input conditioning interfaces.

FPGA Scope Characteristics

The FPGA Scope uses the FPGA-based Acquisition Module from RT-XSG. It is available in any PCIe-based OPAL-RT Board, for which an OPBIN-format bitstream is provided. The acquisition module uses the PCIe interface between the simulator and the Board's FPGA to transmit the acquired signals. The acquisition module has these limitations:

• A list of signals internal to the FPGA available for acquisition is built automatically during bitstream generation and provided to the FPGA Scope.

• From that list, the user selects a subset of signals that would be interesting to visualize during the real-time simulation. This selection is performed prior to loading the model onto the simulator.

• The maximum number of signals that can be simultaneously recorded is limited and is bitstream-dependent. This limit is generally equal to 32 signals.

• The acquisition rate can be adjusted on the fly.

• The minimum acquisition period depends on the number of signals selected and the FPGA user-model clock period. In general, the minimal acquisition period is equal to N+1 clock cycles, where N is the number of signals selected for acquisition.

Procedure

Setup and connections

The I/O interfaces for this model are as follows:

To observe results similar to the behavior described in this document, a loopback connection must be placed between the digital output and input interface for channels 00 to 15, and between the analog output and input interface for channels 00 to 15.

Model preparation

After the ECF model is opened into the HYPERSIM Workspace, prepare the model as follows:

• In the I/O Interface Configuration interface, verify that the Bitstream configuration file corresponds to your hardware

  • The project is provided with firmware intended for OP4510-325T (TE0741_3) and OP4510-410T (TE0741_4).

  • If a new configuration file has been selected, you may need to confirm I/O Configuration in the OPAL-RT Board configuration.

    • Slot 1A - Digital in/Channels 0 - 7 is enabled, with Digital type "Pulse width modulated"

    • Slot 1A - Digital in/Channels 8 - 15 is enabled, with Digital type "Pulse width modulated"

    • Slot 1B - Digital out/Channels 0 - 7 is enabled, with Digital type "Static"

    • Slot 1B - Digital out/Channels 8 - 15 is enabled, with Digital type "Pulse width modulated"

    • Slot 2A - Analog in/Channels 0 - 7 is enabled

    • Slot 2B - Analog out/Channels 0 - 7 is enabled

• In the I/O Interface Configuration interface, make sure that the OPAL-RT Board Chassis ID corresponds to the one of your hardware.

• In the Simulation Settings interface, assign the simulation to your OP4510 simulator.

• Start the simulation

Signal selection

The signals are selected by editing the FSD file associated with the Bitstream configuration file, as is the signal to be used as a trigger for the acquisition. This file is located in the HYPERSIM project directory, within the "firmware" folder.

• In the FSD file, the list of available signals is presented as well as information about their numerical data type, in the JSON format. The selection of signals is made by assigning the value true to the field "Selected" of each signal.

• The maximum number of signals that can be selected simultaneously is indicated as the "max_count_selected_signals" attribute at the top of the FSD file.

• The signal used as the trigger for the acquisition can be assigned by adding a "TriggerSelected" attribute to a signal, with the value true.

In ScopeView, when using the FPGAScope data source, the fsd file will be edited based on the signal selection and trigger configuration, and then sent to the target to be applied during the simulation.

Acquisition

The simulation is executed and then the signals acquired by the FPGA Scope are visualized in ScopeView, following this procedure:

• In HYPERSIM, start the simulation.

• Open ScopeView (See HYPERSIM Ribbon Options)

• Load the ScopeView template next to the .ecf of the model.

• Replace the Data Source by selecting the simulator IP address in the "Target" field of the FPGAScope tab, then click "Fetch Simulation".

• In the "Signal Groups" list, select the simulation matching the model.

• In the signal selection interface, select the signals to be visualized.

• In the ScopeView oscilloscope interface, the trigger signal configuration is displayed. Adjust the acquisition period and window size, trigger characteristics, and then run an acquisition by clicking the black "Start" button.

Open

Measurement of the latency and noise level in the analog interfaces

For this test, the analog inputs and outputs of channels 0 to 3 are selected and superimposed to show the latency induced by the analog conversion cards used across the loopback connection.

In the figure below, the output of the Simulink-based sine-wave generators can be seen. They appear to be sampled at the simulation model rate. By zooming in, one can observe a certain latency between that analog output and the feedback on the analog input for each specific channel. It is also possible to see the difference in the value of the signals, as well as the noise level.

Visualization of the enhancement in precision of the FPGA-based pulse-width modulators

For this part of the demo procedure, the digital outputs of channels 0 to 15 are selected and grouped by common carrier frequency and duty cycle to highlight the difference of accuracy in the modulation between the simple Simulink-based modulators (channels 0 to 7) and FPGA-based modulators (channels 8 to 15).

In the figure below, the output of the HYPERSIM-based pulse-width modulators can be seen (channels 0, 2, 4, 6) as well as the output of the FPGA-based modulators (channels 8, 10, 12, 14). For the lower carrier frequencies (channel pairs 0 & 8 and 2 & 10) the difference in precision is not visible, but for higher carrier frequencies, the precision of the FPGA-based modulators can be fully appreciated.

Measurement of the latency in the digital interfaces

For this test, the digital outputs on channel 0 and the digital input on channel 0 are selected and grouped to evaluate the latency induced by the digital output and input conditioning interfaces across the loopback connection.

The latency for the digital interface loopback should be much shorter than the one of the analog interface loopback. With the signals selected in this example, we can lower the acquisition period down to approximately 100 ns. To acquire at a faster rate, follow this procedure:

• In HYPERSIM, stop the simulation

• Edit the FSD file, setting the "Selected" attribute of all signals of the analog output and analog input interface to false, leaving only the channels of the digital input and output interfaces to true.

• In HYPERSIM, start the simulation again

• In ScopeView, the Acquisition period can now be lowered as low as 15 nanoseconds.

• Run an acquisition by clicking the "Start" button.

• By zooming in, the latency can be observed more precisely. Depending on the type of digital interface, it should be between 30 and 600 ns.