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Objective

Validate the basic operation of Festo inverter connected to a RL load.

Description

This section presents the CPU model and test procedure for testing the inverter with RL load.

Model Overview

The RT-LAB model depicted in figure 1 consists of two subsystems:

• The “SM_OP5707” subsystem includes the model that runs on the real-time simulator

• The “SC_Offline_User_Interface” subsystem presents the user interface that runs on the host PC.

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Figure 1: RT-LAB model overview

The subsystem consists of three areas as shown in figure 2.

• The blue area (Inverter Control) enables the PWM signals (Enable Inverters) of the inverter module, sets it switching frequency (Inverters Switching Frequency), and adjusts its modulation index (Inverter modulation amplitude)

• The gray area (Signal Monitoring) is the block for receiving and monitoring data from the OPAL-RT simulator

• The orange area also provides important information regarding the test instructions

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Figure 2: Contents inside the SC_Offline_User_Interface subsystem

This subsystem consists of three main areas, including “OP8219 and OP8662 IO Interface,” “SIMULATION MODEL BASED ON MATLAB’S ‘UNIVERSAL BRIDGE’ BLOCK,” and “SIMULATION MODEL BASED ON ‘RT-LAB 2-LEVEL TSB’ BLOCK” as shown in figure 3.

• The orange area is used to interface the PWMs besides the voltage and current measurements.

• The blue and yellow areas are respectively used to implement the model in MATLAB and the real-time simulator.

• Both real time and MATLAB models are compared with the results measured from the test bench.

Test Procedure

• The connections of the OPAL-RT OP5707 to the OP8662 and OP8219 are demonstrated in figure 4 and must be performed as shown.

• The connections of the Festo 8857 inverter, OPAL-RT OP8662, and OPAL-RT OP8219 are illustrated in figure 5 and the user must respect the direction and location of the measurement depicted.

•  The control connections (PWM) using the provided DB9 cables between OPAL-RT OP8219 and Festo 8857 inverters is also presented in figure 6.

• Ensure that all power source outputs are off

• Connect the system power circuit and connection signals as shown in figure 4 to 6

• Launch RT-LAB

• Import model zip file (see below) in RT-LAB

• Build, load, and execute the model

• Power on the OPAL-RT OP8662

• Ensure that the power adaptor is connected to the OP8219.

• Ensure that the Festo inverter modules 8857 are powered on using the 24 V AC voltage provided by the Festo power supply 8525.

• Ensure that the 120 Ω resistive load 8509 is switched on.

• Ensure that the jumpers are always installed on the OP8219 board.
  For all tests involved using OP8219, the jumpers need to be installed, unless otherwise stated.

• Ensure the Festo power supply unit 8525 is powered on and the voltmeter’s selection knob is set to DC 7-N.

• Launch RT-LAB

• Import model zip file in RT-LAB

• Build, load, and execute the model

• Increase the variable voltage knob to establish a DC voltage level of 100 V.

• Enable the PWM signal for the 3-phase converter that is being tested, by using the toggle switch from ’0′ to ’1′.

• The modulation reference for the Festo 8857 inverter is set to ’0.12′ as shown in figure 14.

• The switching frequency reference for the Festo 8857 inverter is set to ’4000′ as shown in figure 15.

• Ensure the Festo 8857 converter measurements approximately match the ones shown in figure 16. The 8857 inverter measures:

  • AC current of approx. ‘1.6 A’ peak

  • AC voltage of approx. ‘70 V’ peak

• To stop the model:

  • Set the Festo 8857 ‘Inverters modulation amplitude’ modulation reference to ’0′.

  • Disable the PWM signal for the 3-phase converter that is being tested, by using the toggle switch from ’1′ to ’0′

  • Turn the variable voltage knob to ‘0 V’

  • Turn off the Festo bench

  • Reset the model in RT-LAB.

Conclusion

Based on the preceding tests, the hardware, and the software included in Festo inverter connected to a RL load model are declared fully functional and compliant with OPAL-RT specifications.

Model (Zip File)