Use Case 3 Inlined Thyristor Valve Compensation in SSN

The Inlined Thyristor Valve Compensation (ITVC) method is a real-time method to compensate for the sampling effect of thyristor by the fixed step time frame.

Simply put, each time a thyristor firing pulse is generated, it must wait for the next time step to be taken into account inside the simulation. If the pulse arrives just before the fixed step frame, the error is minimal, but when it occurs just after, the error is bigger because the wait lasts almost a full time-step. Because the firing pulses are not synchronized on the simulation time step, it usually results in a low-frequency jitter on important system variable, often confused with controller instability.

The ITVC method is designed to compensate for this effect, in off-line and HIL simulation. It is so efficient that it is always active in ARTEMiS (State-Space and SSN).

Note: For the ITVC method to work properly, all thyristors must have a non-null Voltage Offset in the parameters, otherwise a warning appears.

We now explain the ITVC method on the HVDC example with 6 groups, 11 nodes SSN separation.

In the model, a Firing Pulse Unit was designed with RT-EVENTS.

The RT-EVENTS blockset keeps the in-step events of this type of firing pulse unit with multiple comparators in memory.

Since version 6 of ARTEMiS, the way RT-EVENTS connects to ARTEMiS solvers has been simplified. The ARTEMiS solver now requires only a double value between zero and 1 to activate and compensate thyristors switches. If the value equals only exactly 1 and 0 (as in regular SPS), the simulation is not compensated. But if the value is between 0 and 1, the value is taken as the time ratio of the gate event within the time step. Ex: a value of 0.6 would mean that the event occurred at 60% after the beginning of the time step.

Now, in common models, an RTE converter block does this job as in the following figure.

If the RT-EVENTS compensation item of the block is set to Enabled, the HVDC simulation will also be compensated.

The following figure shows the DC current of the HVDC during energization.

If we now look closer at the IDC current and rectifier firing angle, the effect of the compensation is obvious.

In the above figure, we observe a characteristic low-frequency jitter on both DC-link current and firing angle, quantities linked by the HVDC control. When the ITVC is OFF, there is an approximate 10 Hz jitter on both values not present with ITVC in function. This jitter is typical of fixed-step solvers and would be present in all fixed-step based simulation algorithms (EMTP, PLECS, SPS, PSIM, etc...).