Description

The OP5705XG is a complete simulation system, which contains a powerful target computer, a reconfigurable FPGA, and signal conditioning for up to 256 I/Os.
The design makes it easy to use with standard connectors (DB37, RJ45, SFP, and mini-BNC) without the need for input/output adaptors and allows quick connections for monitoring I/O signals.
It is designed to be used either as a desktop, shelf top, or mounted in a standard 19’’ rack.

Simulator Architecture 

Block Diagram

The front of the chassis provides access to the monitoring interfaces and connectors.
The rear of the chassis provides access to the target computer’s standard connectors the I/O connectors, power cable, and main power switch.

The housing is divided into two sections, each with a specific purpose.

Lower Section

• The lower section of the chassis contains a powerful target computer that can be added to a network of simulators or can act as a standalone. 
• The target computer is used to run simulations built with OPAL-RT’s RT-LAB or HYPERSIM software simulation platform and includes the following features:
  • ATX motherboard
  • OPAL-RTLinux 3.x real-time operating system
  • Intel® Xeon® Scalable Processors - 2nd Generation CPU with 4, 8 and 16 processor cores, up to 3.8 GHz. See Configuration Options below
  • 32 GB of DRAM
  • 500 GB SSD disk
  • Space to install 2 PCI with risers, or 3 PCIe

Upper Section

The upper section contains the high-speed FPGA and the conditioning modules for up to 256 I/Os.

It includes:

• A Xilinx® Artix®-7 FPGA programmable from the target computer via PCIe.
  • The FPGA is used to execute models designed with the OPAL-RT RT-XSG toolbox, manage the I/O lines and execute embedded FPGA-based simulations.
  • It exchanges data with the real-time simulations running on the target computer CPUs via the PCIe link, an 8-slot flat carrier board capable of connecting any combination of up to 8 digital and analog conditioning modules.
• 8 digital and analog conditioning modules:
  • Each module controls 16 or 32 lines for a total of up to 256 I/O lines.
• 4 SFP ports for high-speed communication with other FPGA-based systems or with external devices.
  • The standard communication protocols available with the OP5705XG are based on Xilinx Aurora (1 to 5 Gbps).
  • Other protocols, such as the Gigabit Ethernet, can also be implemented.
  • These SFP ports can be used to expand the simulator I/O capabilities using OPAL-RT’s MUlti-System Expansion link (MuSE):
    • Each port can be connected to one OPAL-RT remote I/O unit (OP4520, OP5607, OP5650, OP5705-IO, OP5707-IO), effectively increasing the simulator I/O capability to a maximum of 1024 channels.
    • SFP ports not used for MuSE remain compatible with the legacy Generic Aurora link.
    • The MuSE link is compatible with OPAL-RT boards I/O management architecture.

Configuration Options

The OP5705XG is available in a number of different configurations that make it easier to integrate into your environment: