Introduction

This block packs data according to the timing and data format of protocol. For each fiber optic channel one TXInterface block should be placed in the model.

Mask and Parameters

Name	Description
Counter Width	Number of bits for the internal counter representing number of data in one packet.
Sample Period	FPGA clock cycle.

Inputs, Outputs

Inputs

Name	Description	Number Format
Enable	Enable signal from fiber optic channel driver block.	Boolean
TX_READY	Signal showing fiber optic channel is ready to send data. This signal is sent by fiber optic channel driver block.	Boolean
SendPeriod	Sending interval between packets in terms of number of FPFA clock cycle.	UFIX16_0
NbrData	Number of data in one packet.	UFIX9_0
Din	Data being sent in packet. Note: Din reads i-th data if TX_DATA_INDEX is i at the pervious clock cycle.	UFIX32_0

Outputs

Name

Description

Number Format

TX

Data packet being sent. This output includes the following signals:

vld: valid bit

data: data being sent

eof: end of frame signal.

vld: boolean

data: Ufix32_0

eof: boolean

TX_DATA_INDEX

Counter signal counting from 0 to NbrData (input of block) every sending period when both Enable=1 and TX_READY=1.

Note 1: TX_DATA_INDEX increase from 0 to NbrData.

Note 2: There is one FPGA clock cycle delay between TX_DATA_INDEX and Din, meaning i-th data sent to Din when TX_DATA_INDEX is i at the pervious clock cycle.

UFIX9_0

Description

In normal condition, both Enable and TX_READY received from SFP driver should be "1". Also, if packets are sent from internal of the model, both of these signals should be kept "1" to mimic SFP signals in normal condition. For each SFP channel one TXInterface block should be placed in the model. In this block, the data packet being sent should be in Ufix32_0 format.

MMC User Documentation

TXInterface Block

Introduction

Mask and Parameters

Inputs, Outputs

Inputs

Outputs

Description