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Test Design for Half Bridge Topology
The first part of the test is based on half-bridge sub-module topology, shown below:
For thorough, reliable tests, eight kinds of tests are designed:
Maximum cell number test
Vcap observation and Gate Signals block test
Vcap modes test
Pulse source test
Fault mode test
Cell capacitance test
Resistance in shunt with the cell capacitor test
Switch Ron test
At the beginning of each designed test, the system should be initialized.
Initialize the Parameters of MMC Parameter Block
MMC parameter block initialization setup
Variable | Set value | Reason |
|---|---|---|
SM Type | 0: Half-bridge | Tests designed for Half-bridge topology |
cell capacitance (farads) | 0.01 | A test value, may vary |
switch Ron (ohms) | 0 | Remove voltage drop on Ron |
capacitor shunt resistance (ohms) | 1e12 | Disable discharge by Rshunt |
Number of cell per arm | 10 | Total number need to be tested |
[Sb Vb] power and voltage bases | [10 10] | So for each cell, the SI and PU values are the same, i.e. 1 A is 1 pu for current and 1 V is 1 pu for voltage. |
Vcap mode | Set to fixed value | To initialize and fix the Vcap=Vcap value |
Vcap fix value (pu) | 0 | To initialize and fix the Vcap=0 |
Pulse source | Direct gate signal from CPU | Control cells using Gate Signals block |
Initialize the Parameters of Arm Current Generation Block
Arm Current Generation block initialization setup
variables | Set value | reason |
DC current | ones(6,1)*0.1 | Some tests need an arm current pulse with magnitude of 0.1 and duration of 0.01 s. this initialization can generate this arm current easily.
|
AC magnitude | ones(6,1)*0 | |
Frequency | ones(6,1)*50 | |
Form of the current | 1.Current with a duration | |
Pulse duration | ones(6,1)*0.01 |