(Archived) eHSx64_PMSM_VDQ_IO_7868R

This Hardware Configuration has been archived and should not be used in new projects. Please contact OPAL-RT Support for more information.

Specifications

This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.

Quantity	FPGA Board

Quantity	FPGA Board
1	PXIe-7868R

The PXIe-7868R supports the following features:

IO Type	Details

IO Type	Details
Analog Input	6 CH, 1MS\s, 16-bit, +/- 10V Input Signal Range, Differential Tunable Gain, Offset, and Min/Max Saturation
Analog Output	18 CH, 1MS\s, 16-bit User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation. Measurements Sinewaves CPU (VeriStand) Resolvers
Digital Input	32 CH, 80MHz, 3.3V TTL (Connector 1)
Digital Output	16, 10MHz, 3.3V TTL (Connector 0) User-defined mapping to Digital Outputs available with tunable Polarity. CPU (VeriStand) Encoders Hall Effect PWMs Digital Inputs

This configuration includes a pre-compiled firmware/bitfile which contains the following features:

Features	Additional Information

Features	Additional Information
1x eHSx64 Solver	User-defined mapping to Circuit Sources available: CPU (VeriStand) Sinewaves PMSM Analog Inputs User-defined mapping to Circuit Switches available: CPU (VeriStand) PWMs SPWMs Digital Inputs
1x PMSM Variable Parameter Solver	Refer to PMSM VDQ Section (Archived) for more information.
1x Resolver	The excitation signal for the resolver is directly connected to the AIO channel. This connection is not assignable. In addition, the excitation signal must be scaled appropriately such that it has an amplitude of -1V to 1V.
1x Encoder	Assignable to any DO port
1x Hall Effect Sensor/motor	Assignable to any DO port
32x Sinewave Generators
16x PWM Generators
12x Sinusoidal PWM Generators
Analog Output Mapping and Rescaling
Analog Input Rescaling
32x Waveform Acquisition Channels