Documentation Home Page Power Electronics Add-On for NI VeriStand Home Page
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

(Archived) RCP_IO_7861R

Specifications

IO Capabilities

This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.

Quantity

FPGA Board

Quantity

FPGA Board

1

PXIe-7861R

 

 

The PXIe-7868R supports the following features:

IO Type

Details

IO Type

Details

Analog Input

16 CH, 1MS\s, 16-bit, +/- 10V Input Signal Range, Differential

Tunable Gain, Offset, and Min/Max Saturation

Analog Output

8 CH, 1MS\s, 16-bit

User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.

  • Sinewaves

  • CPU (VeriStand)

Digital Input

8 CH, 10MHz, 3.3V TTL (Connector 0)

Digital Output

24 CH, 10MHz, 3.3V TTL (Connectors 0 and 1)

User-defined mapping to Digital Outputs available with tunable Polarity.

  • CPU (VeriStand)

  • SPWMs

  • PWMs

  • Digital Inputs

 

Refer to 7861R IO Pinout [RCP_IO_7861R] to see the IO assignment.

Modeling Capabilities

This configuration includes a pre-compiled firmware/bitfile which contains the following features:

Features

Low Latency Support

⚫ = Supported   ⚪ = Not Supported

 


In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter