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Synchronization

Description

This document explains how to use the Synchronization driver to return a timestamp to the model and perform different synchronization scenarios. The actual driver only supports the Oregano Syn1588 PCIe card but additional hardware may be supported in the future.

The Oregano Syn1588 card is continuously generating a clock signal on one of its external signal connectors. The period of this signal is set by the timestep of the model; this signal can be physically connected to the FPGA to synchronize the simulation. The second external connector can be used to either synchronize the card from an external IRIG-B or 1PPS signal or to generate an IRIG-B or 1PPS signal.


The following operation modes are possible:

Operate as an IEEE-1588 slave mode synchronized through the network by an external IEEE1588 master

and one of the following options:

  • Do not generate any external signal
  • Generate an IRIG-B signal
  • Generate a 1PPS signal

Operate as an IEEE-1588 master node to synchronize external IEEE1588 slave nodes on the network

and one of the following options:

  • Do not generate any external signal
  • Generate an IRIG-B signal
  • Generate a 1PPS signal

Operate as an IRIG-B slave node synchronized through an external IRIG-B signal

and one of the following options:

  • Do not perform any IEEE1588 operation
  • Operate as an IEEE-1588 master node to synchronize external IEEE1588 slave nodes on the network

Operate as a 1PPS slave node synchronized through an external IRIG-B signal

and one of the following options:

  • Do not perform any IEEE1588 operation
  • Operate as an IEEE-1588 master node to synchronize external IEEE1588 slave nodes on the network

The driver is initialized when the model is loaded. A synchronization process launched in the background will begin to lock on either a PTP, IRIG-B or 1PPS input depending on the user configuration. A timeout can be defined to make sure good quality of synchronization is achieved. Once this timeout expires, the synchronization output pulse is generated. The first rising edge of this synchronization output pulse will be aligned on the rising edge of the 1PPS reference signal disregarding if this reference signal comes from PTP, IRIG-B, or 1PPS input.

When the model execution begins (i.e from pause mode to run mode), if the option is enabled, the first model step can be blocked until the beginning of the next second. This allows the simulation to always begin aligned with the beginning of a new second. This feature can be very interesting in power system simulations where several types of equipment are synchronized with the same time reference.

Supported Features

The following is a list of the features supported by this driver:

  • Operate as an IEEE1588 master or an IEEE1588 slave node
  • Supports IEEE-1588-2002 (PTP V1) and IEEE-1588-2008 (PTP V2)
  • Supports all standard profiles:
    • Default (IEEE1588-2008 Annex J.3)
    • Default P2P (IEEE1588-2008 Annex J.4)
    • Power (C37.238 2011)
    • Power S (C37.238 2011 slave only)
    • Power 2 (C37.238 2014) - only supported on 32-bit Linux platforms (x86)
    • Power 2 S (C37.238 2014 slave only) - only supported on 32-bit Linux platforms (x86)
    • C37.238 2017 - not supported on 32-bit Linux platforms (x86)
    • C37.238 2017 - not supported on 32-bit Linux platforms (x86)
    • SMTPE (ST 2059-2)
    • SMTPE  S (ST 2059-2 slave only)
    • Telecom (G.8265.1 master only)
    • Telecom2 (G.8275.1)
    • Telecom2 S (G.8275.1 slave only)
    • gPTP (IEEE 802.1AS-2001)
    • gPTP S (IEEE 802.1AS-2001 slave only)
  • Generate demodulated IRIG-B or 1PPS signal to synchronize external devices
  • Can be synchronized by an external IRIG-B or 1PPS signal
  • Implements best-master-algorithm defined in the IEEE1588 standard based on the configurable priority
  • Supports virtual LANs (VLAN)
  • Supports peer-to-peer and end-to-end delay mechanisms
  • Starts the simulation aligned to the 1PPS reference (next second change)

These features are detailed in the next section.

Driver Configuration

The driver is entirely configurable via the RT-LAB GUI within a general configuration panel.

General configuration

HardwareThe only supported hardware for the moment is the Oregano Syn1588 PCIe card.
Enable verbose modeIf set to "true", additional information will be displayed on the RT-LAB monitor during the load of the model
Synchronization mode

Select if the card will be synchronized from PTP, IRIG-B, or 1PPS. When configured in PTP mode, the driver can operate as a PTP master or a PTP, slave.

The operation mode depends on the selected PTP profile and priority. When configured in IRIG-B or 1 PPS mode, the driver will expect to receive a valid signal on the external SMA connector. In this mode, the driver can also operate as a PTP master to synchronize other PTP slaves on the network.

Generate sync signalThis option is only available when the external synchronization mode is PTP. When operating in PTP mode, the external SMA connector can be used to generate a,1 PPS or an IRIG-B signal.
Wait for next secondWhen enabled, the beginning of the simulation will be delayed until the next second change. The rising edge of the synchronization signal will be aligned with the rising edge of the 1 PPS signal in either PTP, IRIG-B or 1 PPS mode. If this parameter is disabled, the simulation can begin in the middle of a second.
Wait for synchronization timeout (seconds)The synchronization process will begin once the model is loaded but the simulation will not begin until the timeout configured by this parameter has expired. This parameter should be tuned to make sure the simulation is started with a good synchronization with the external source. To begin the simulation immediately after the model is loaded, set this parameter to zero.
Network interface

This field is not mandatory, it can be left blank or set to "auto" to allow the software to automatically discover the network interface.

Otherwise, this parameter must match with the network interface name of the IEEE1588 compatible hardware. An error will be displayed at load time in case that the network interface is not supporting PTP.

PTP profileSelect the PTP profile that matches your architecture. A PTP profile specifies a preset of IEEE1588 configurations and operation mode. For more information, please consult the IEEE 1588-2008 standard. Possible options are Default, P2P default, Power, Power slave, Power2, Power2 slave, C37 238 2017, C37 238 2017 slave, SMPTE, SMPTE slave, Telecom master, Telecom 2, Telecom 2 slave, gPTP, gPTP slave
Delay mechanismThe mechanism used to calculate the delays incurred during the propagation of the packets across the network. Possible options are peer-to-peer and end-to-end.
Use VLANSelect this option if the synchronization hardware is connected to a VLAN. In this case, the VLAN identifier needs to be specified.
PriorityThe value chosen for the priority will be taken into account by the Best Master Clock Algorithm (BMCA). A lower value means a higher priority. If the IEEE1588 card is operating in master mode and another device with a higher priority appears, on the network, the simulator will become a slave.
Advanced optionsThe Oregano Syn1588 PCIe card has the possibility to handle very specialized configurations. This field is there to open custom configurations in case it is required for some customers. This field should only be used by advanced users or with the help of Opal-RT's support team.
Time offset (s)The time offset to apply on the timestamp read from the hardware, expressed in seconds. This parameter accepts values with precision up to the nanosecond. If set to an non null value, the driver will output the original time as well as the shifted timestamp.


If the clock is not well synchronized (timestamp starting at 0 seconds) the original clock may be compensated to avoid a negative shifted timestamp.
Apply this configuration automatically next time the system boots

If enabled, the card will be configured by an OS service launched at boot time. This will provide a stabilized offset with the Grandmaster clock at the beginning of the simulation.


This feature is not supported on 32-bit Linux platforms (x86).

Enable virtual mode

In virtual mode, the model can be executed even if this I/O interface is not compatible with the hardware configuration of the system. The connections between the model and the I/O interface will be done during the initialization, but the I/O interface will not do anything. The virtual mode can be used to troubleshoot problems on a system without having the required hardware, or to prepare a model with different I/O interfaces even if the final hardware platform is not available.

Connections

Once the driver has been configured as desired, the user can connect some data points from the driver to the model by using the designated RT-LAB GUI. The connection panel will show all the connectable points (from both, the driver and the model), once the model has been compiled. It is also possible to make connections on LabVIEW panels. Connections are easily made by drag-and-dropping connectable onto each other.

The following data points can be connected to the model to provide the timestamp and additional information about the state of the synchronization:

Connection pointDescription/range
Time/SecondsProvide the number of seconds elapsed since 00:00:00 of January 1st, 1970 (UTC). This number is also known as Unix time, POSIX, time or Epoch time. This number begins at 0 at the moment the card is powered on and increases at each second. If the Oregano Syn1588 PCIe card becomes synchronized by an external IEEE1588 PTP master or by an external IRIG-B signal, this value will suddenly change to the time provided by the external equipment.
Time/Nanoseconds

Provide the number of nanoseconds within the actual second. This number varies from  to  (exclusive) at each second.

Shifted time/Seconds

Provide the shifted timestamp in seconds obtained from the 'Time offset (s)' parameter applied on the Time/Seconds connection point.

This connection point is only available if the 'Time offset (s)' parameter is non null.

Shifted time/Nanoseconds

Provide the shifted nanoseconds obtained from the 'Time offset (s)' parameter applied on the Time/Nanoseconds connection point. This number varies from to  at each second.

This connection point is only available if the 'Time offset (s)' parameter is non null.

Info/PTP Sync StateThis data point provides information about the state of the synchronization:
1 Initializing: The card is not ready yet
2 Faulty: Should never happen. Contact Opal-RT support
3 Disabled: Should never happen. Contact Opal-RT support
4 Listening: Waiting to be synchronized
5 PreMaster: Initializing master mode
6 Master: Operating as an IEEE1588 master PTP node on the network; can be synchronized through IRIG-B or 1PPS
7 Passive: IEEE1588 is not activated; the card is synchronized through IRIG-B or 1PPS
8 Uncalibrated: Attempting to lock on external synchronization source
9 Slave: Operating as an IEEE1588 PTP slave node on the network
Info/PTP Slave OffsetThis data point only provides information if the card is operating as a PTP slave (state 9), which means it is synchronized by a PTP master. It gives information about the offset with the master clock calculated at each second by the PTP protocol algorithm. A low number indicates a good synchronization with the PTP master clock. All the network equipment between the PTP master and the Oregano Syn1588 PCIe card must be IEEE15888 compliant to have a good synchronization.
Info/Sync AccuracyIn PTP mode, this data point provides information about the accuracy of the PTP master clock. As an example, if the PTP master clock is operating on its local oscillator without any external reference, the accuracy can be 100000 nanoseconds (depending on the equipment). And when this PTP master clock acquires external synchronization with a GPS antenna, as an example, the accuracy will change to 100 nanoseconds.
If the Oregano Syn1588 PCIe is synchronized by a good IRIG-B or 1PPS signal, the accuracy can reach 25 nanoseconds.

The example project packaged within RT-LAB shows how to connect these data points to the model. Import the whole project and not only the model to have pre-routed connections on the data points.

  • Examples\IO\Oregano\Oregano_syn1588

Limitations

The current version of the driver has the following limitations:

  • The Oregano Syn1588 PCIe card accepts demodulated IRIG-B004 or IRIG-B007 signals (3.3V) only.
  • The Oregano Syn1588 PCIe card can generate IRIG-B007 or 1PPS signals (3.3V) only.
  • On 64-bits Linux platforms, the firmware version number must be greater than 808.

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