Time Step

Simulation Time Step. Must be between 50 ns and 4000 ns.

General: The eHS solver will use the time step provided at his best and throw an error at build whether the value does not meet the minimum time step.

Default: The solver will use the minimum time step achievable with the given circuit.

Parameter set storage management

Choose your preferred scenario feature.

From CPU (Default): updating to a new set of data is done over multiple time steps, in a few milliseconds. Number of scenarios is not limited.

From FPGA (Default): updating to a new set of data is done in a single time step. Number of scenarios is limited and depends on the size of the circuit.

Reset Pin

Add an input and ouput reset pin

Input Reset value range

• [0;1[ gives no reset

• [1;inf[ is maintaining a reset on all part of the circuit

Output Reset is a feedback

Circuit analysis method

Method to analyze the electrical circuit.

Default: Gen4 is the official method. Gen5 is still in beta.

Solver strategy

Allows to choose to minimize eHS Time Step or the latency between eHS and other components.

Allows to enable High Performances option for best achievable Time Step

Standard: Time step down to 200ns.

High Performance: Unlocks time step down to 90ns and interpolation on switching events, optimizing performance and precision, ideal for higher switching frequencies above 100kHz for topologies such as resonant converters and DAB.

How to choose Solver Strategy (Smallest Time Step vs Lowest Latency)

Discretization methods

Each circuit analysis method offers different discretization capabilities.

Gen4: offers only Backward Euler method.

Gen5: offers both PADE5 and Backward Euler methods.

Switch interpolation

Allows to sample gates at a higher rate than the discretization Time Step.

Each circuit analysis method offers different switch interpolation capabilities.

Time factor scale

Allows the user to do slower than real time simulation for fast dynamic circuits.

Currently not yet supported.