Description

The current functionality is used to receive raw data asynchronously by an RT-LAB model from an OPAL-RT card. This is achieved by using the LoadOUTports of the FPGA.

As opposed to DataOUT, the transfer of LoadOUT data is relying on a slower communication link between the FPGA and the CPU and is not meant to be used at every step of the simulation. Doing otherwise leads to decreased simulation performances.

The main purpose of this functionality is to transfer data on an as-needed basis from the FPGA to the CPU. An example of such use would be to validate that configuration-type data sent to the board through LoadIN ports was done successfully. The transfer is done during the execution of the simulation (with the help of a trigger mechanism). Please check the Usage section below for details on how the trigger mechanism is to be used.

In the RT-XSG implementation, the bitstreams have 32 LoadIN input ports and 32 LoadOUT output ports. Each port has a maximum width of 250 32-bit data words. These ports are used to exchange data asynchronously between the RT-LAB model and the FPGA chip of the card.

Usage

Once the bitstream configuration file has been parsed, the ports capable of asynchronous raw data transfer are revealed to the user.

If the bitstream offers the possibility of transferring raw data asynchronously from the FPGA to the CPU then a new section named Load from the board will appear as a subsection of General. There, a dedicated configuration page will be created for each usable port, based on the information parsed from the bitstream configuration file. The title of each port's configuration page will contain the port number (count starting from 0)and the maximum number of DWORDS serviceable.

By clicking on a port's configuration page, the user will be able to define the data frame expected from the FPGA. This can be achieved by adding, removing and/or moving signals up or down in the data frame table using the buttons found above the table. The configurable parameters of each signal are detailed in the section below.

Adding a signal to the data frame table will also add a connection point for it in the Configuration panel of RT-LAB.

In this scenario, if the table element has a vector size different from 1 (see the section below for a description of the Vector size parameter), then its connectable item in the Configuration panel is an array.

If there is at least one signal to be received, the trigger connectable point is also added to the Configuration panel.

For receiving data from the FPGA, connections must be made between the points in the model and the raw data connectable points. For the data, the model points take the form of OpInput blocks. For the triggers, OpOutput blocks have to be used.

In order to achieve that, the connection point for each signal (or array of signals) and each trigger must be drag-and-dropped onto an appropriate OpInput or OpOutput blocking the Configuration panel of the RT-LAB project.

Connections with LabView panels are also possible.

Once the simulation is executing, data transfer will occur when the trigger's value will pass from '0' to '1' (rising-edge detection). Leaving the value of the trigger at'1' will not allow for data transfer.

Signal configuration

Name

The name of the signal (or vector of signals) is important as it is the name given to the interface's connectable point.

Type

The type is selectable from a drop-down list. The options are Bit, Unsigned, Signed, Float and Double. They represent the encoding to be used when interpreting data received from the FPGA.

If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Certain types force other parameters to change their value to a fixed one:

• The Bit encoding forces the Size (bits) parameter to 1
• Float forces the Size (bits) parameter to 32 and the Bit offset parameter to 0
• Double forces the Size (bits) parameter to 64 and the Bit offset parameter to 0

Vector Size

Setting this parameter different from 1 will result in the interface creating an array of signals starting at the byte offset specified. Each element of the vector will have the type, size, minimum and maximum values as specified in its table entry. The name of the connectable created for the vector will be the one specified at the parameter Name.

Using vectors can be beneficial when a data frame has contiguous signals that have the same parameters because it reduces the time necessary to configure the interface.

Keeping the value at 1 will maintain the current signal as an individual element of the data frame.

Current constraints are related to vector elements having to be aligned on byte-boundaries:

• The Bit offset parameter cannot be different from 0
• The Size (bits) parameter must be one of the standard data type sizes (i.e. 1, 8, 16, 32 or 64)
• In the case of Type being set to Binary, the maximum vector size is 8

Byte Offset

This parameter represents the byte offset within the load port from where the current table element will be read.

Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click the check-mark icon found next to the subsystem association drop-down, in the interface's view.

Bit Offset

This parameter represents the bit offset within the byte specified at the Byte offset parameter for the current table element.

Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click on the check-mark icon found next to the subsystem association drop-down, in the interface's view.

The Bit offset cannot be used (i.e. it is grayed out) for Float and Double signal types. It also can't be used in case the table element is a vector (i.e. Vector size is greater than 1).

Size (bits)

The Size (bits) parameter is where the size in bits of the current signal can be specified.

The size is fixed to 1 for Bit types, to 32 for Float types, and to 64 for Double types.

The maximum size allowed by the interface is 64 (which is the size of the largest native data type).

If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click on the check-mark icon found next to the subsystem association drop-down, in the interface's view.

Min

The minimum value that will be reported in the Simulink model or LabView panel for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Note that the value given by the FPGA could be lower than the minimum. In this case, the interface will report the minimum.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the minimum cannot be less than-128 (the smallest signed integer representable on 8 bits).

The current limitation of this parameter is that it is not applicable for Float and Double types.

Max

The maximum value that will be reported in the Simulink model or LabView panel for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Note that the value given by the FPGA could be greater than the maximum. In this case, the interface will report the maximum.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the maximum cannot be greater than127 (the largest signed integer representable on 8 bits).

The current limitation of this parameter is that it is not applicable for Float and Double types.

Characteristics and Limitations

In order to correctly configure the data frames for each port, the user must have knowledge of how data on the ports of interest is generated by the logic implemented in the bitstream.

The current version of the asynchronous raw data input functionality of the OPAL-RT Board driver has the following limitations:

• The bit offset cannot be 0 when the vector size is greater than 1
• The size (in bits) must be standard (i.e. 1, 8, 16, 32, or 64) when the vector size is greater than 1
• The maximum vector size is 8 for the binary data type
• The bit offset cannot be used for any signals of type float or double (i.e. these types of data must be byte-aligned)
• The minimum and maximum parameters are not applicable for signals of type float
• The minimum and maximum parameters are not applicable for signals of type double