Inverter Simulation with Time Stamped Bridge TSB Inverter Block

The circuit shows the capability of ARTEMIS to accurately simulate PWM inverter circuits with a TSB inverter block (TSB: Time-Stamped Bridge)

This model uses a TSB inverter block to model the inverter of the circuit. In that case, the interpolation is made locally inside the TSB and not on the complete state-space system of the electric model.

TSB Features

TSB model supports modes with no IGBT pulsing.

TSB model supports deadtimes smaller than simulation time step (E.g. in this demo there is a 5 us deadtime in the IGBT pulses). This is a feature not supported by ANY SPS models (detailed, switching function or averaged).

Notes

ARTEMiS inlined TSB model can be used for this case. TSB model is embedded within the SSN solver in this case and the method is called IVIC (Inlined Voltage Inverter Compensation).

Open this Example with IVIC method