ARTEMiS Switch Primer Selecting the Switch Model/Method/Solver

This section will help users select the proper switch model and/or method and/or solver.

TSB and TSB-RD	TSB stands for Time-Stamped-Bridge; these are interpolating switching functions which interface directly with Time-Stamped Digital Inputs in HIL applications or RT-EVENTS in offline mode. TSB-RD is the latest generation of TSB. RD stands for real-diode and these diodes simplify the management of passive modes like high-impedance or natural rectifying modes. Their main drawback is that they use real SPS diodes. This means that in applications with several topologically connected inverters, the user must use SSN to decouple without delays the switches in order to avoid memory overflow caused by matrix precalculations. Standard TSB mimics these passive modes by implementing a diode model with a PID and they require artificial RC snubbers for stability. TSB and TSB-RD can simulate PWM drives at very low Fs/Fpwm rates (3.3 in Ttype_TSB_2rates.slx, a PV application demo with T-type inverters, in the ARTEMiS demo path). Fs is the sampling frequency. TSB and TSB-RD notably support deadtime smaller than the sample time, something that SPS switching functions do not.
Inlined Voltage Inverter Compensation (IVIC)	This is an ARTEMiS-SSN built-in algorithm that simulates 2-level and 3-level NPC inverter with high precision, much like TSBs. The main difference of IVIC is that it does not create any delays between the DC and AC sides of the inverters. This delay is not important in most applications. But sometimes, like in the ARTEMiS-SSN Inlined Time-Stamped Bridge in 2-level VSC-based HVDC applications demo, this delay creates some oscillations with TSBs. The main drawback of the IVIC inverter is that it is limited to Fs/Fpwm greater than 10 (i.e. if your simulation time step is 10µs (Fs=100kHz), then your PWM frequency cannot exceed 10 kHz).
iSWITCH (SSN-Iterative Switch model of SSN)	iSWITCH switches (diode, thyristor, IGBT/GTO/MOSFET, IGBT-diode, etc...) are regular SPS switches. When put into an SSN group, alone and with V-type NIB, the SSN algorithm will simulate them with iterations, ensuring the highest accuracy. The main drawback of using iSWITCH is that iterations can lead to longer real-time simulation sample time. Additionally, since all switches must be in a unique SSN group, the SSN group choice may not be optimal.
Inlined Thysistor Valve Compensation (ITVC)	This is a compensation algorithm for thyristor only, working both in HIL and offline modes. The ITVC will very efficiently compensate for thyristor firing events occurring anytime during a simulation time step. Several HVDC demos with ITVC are available in the ARTEMiS demos.

References

C. Dufour, J. Mahseredjian, J. Belanger, "A Combined State-Space Nodal Method for the Simulation of Power System Transients", IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935

ARTEMiS Switch Primer Selecting the Switch Model/Method/Solver

TSB and TSB-RD

Inlined Voltage Inverter Compensation (IVIC)

Inlined Thysistor Valve Compensation (ITVC)