Simulation of Single Thyristor Rectifier with ARTEMIS ITVC Inlined Thyristor Valve Compensation

The circuit shows the capability of ARTEMiS to accurately simulate a circuit with line-commutated switches with the ITVC algorithm. The ITVC is always enabled in ARTEMiS.

Demonstration

Open the model and start the simulation. If you zoom in closer on the load current in steady-state near the end of the simulation, you can observe that the amplitude jitter is about 0.003 A on the peak of the current (the peak is in average 11.02 A).

Now delete the ARTEMiS Guide and re-run the simulation. If you look at the load current again, you observe that the current peaks are much lower and vary in amplitude (jitter).

In regular fixed-step simulations, this jitter phenomenon is caused by the fact that switching events can only be taken into account at time step hit. By contrast, the ITVC option compensates each switching event.

Notes

In some versions of SPS, there is an internal delay in the thyristor gate signal compared to the ARTEMiS solvers. This will cause the average current of the thyristor rectifier (driven in open loop here) to be a little bit lower than seen in the image above.