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Oregano syn1588

The Synchronization I/O interface allows using the Oregano Syn1588 board to return a timestamp to the model and perform different synchronization scenarios. The Oregano Syn1588 card is continuously generating a clock signal, which period is set by the timestep of the model, on one of its external signal connectors. This signal can be physically connected to the FPGA to synchronize the simulation. The second external connector can be used to either synchronize the card from an external IRIG-B or 1PPS signal, or to generate an IRIG-B or 1PPS signal.

With the proper user configuration, a driver is initialized on the target simulator at the start of the simulation. A synchronization process launched in the background will begin to lock on either a PTP, IRIG-B, or 1PPS input depending on the user configuration. A configurable delay can be defined to make sure a good quality of synchronization is achieved. Once this delay expires, the synchronization output pulse is generated. The first rising edge of this synchronization output pulse will be aligned on the rising edge of the 1PPS reference signal disregarding if this reference signal comes from PTP, IRIG-B, or 1PPS input.

If the option is enabled, the first model step can be blocked until the beginning of the next second. This allows the simulation to always begin aligned with the beginning of a new second. This feature can be useful when several equipment or distant simulators are synchronized with the same time reference.

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