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V2.19 Virtex-7 VC707 - eHS x128 - Gen5 - PMSM - IM - PMSM SH - IO Config3

Owned by Fabien Ducat
Sept 11, 2024

OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com

© 2023 OPAL-RT TECHNOLOGIES All rights reserved

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SCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver
  • Two Dual Permanent Magnet Synchronous Machines (PMSM-VDQ) models
  • One Dual Permanent Magnet Synchronous Machines (PMSM-SH) models
  • Two Analog Output Mapping and Rescaling (AOMR) modules
  • One Analog Input Differential Rescaling (AIR) module


LoadIn/DataIn/DataOut mapping

Port

LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3


TSDO 2 - eHS 8 to 15

Digital In 4B - 0 to 7

4

PWM 2B -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 4B - 8 to 15

5

PWM 2B -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 4B- 16 to 23

6

PWM 2B -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 4B- 24 to 31

7

PWM 2B -  24 to 31

TSDO 6 - eHS 40 to 47

Analog In 1B - 0 to 7

8

PWM 2A -  0 to 7

TSDO 7 - eHS 48 to 55

Analog In 1B - 8 to 15

9

PWM 2A -  8 to 15

TSDO 8 - eHS 56 to 63

PMSM VDQ 1/2

10

PWM 2A -  16 to 23

TSDO 9 - eHS 64 to 71

PMSM VDQ 3/4

11

PWM 2A -  24 to 31

Digital Out 2B - SDO 0 to 7

PMSM SH 1/2

12

Config AOMR (1A,3B)

Digital Out 2B - SDO 8 to 15

eHS Period Averaged

13

eHS PWM 1 - eHS 24 to 31

Digital Out 2B - SDO 16 to 23

eHS Period DownSample

14

eHS PWM 2 - eHS 0 to 7

Digital Out 2B - SDO 24 to 31

TimeOn Averaged

15

eHS PWM 3 - eHS 8 to 15

Digital Out 2A - SDO 0 to 7

TimeOn DownSample

16

eHS PWM 4 - eHS 16 to 23

Digital Out 2A - SDO 8 to 15

RMS and Power calculation

17

Config AIR

Digital Out 2A - SDO 16 to 23


18

Config PMSM VDQ 1/2

Digital Out 2A - SDO 24 to 31


19

Config PMSM VDQ 3/4

AOMR (1A,3B) /Analog Out 1A -  0 to 7


20

Config PMSM SH 1/2

Analog Out 1A -  8 to 15


21


AOMR (3A,4A) /Analog Out 3B -  0 to 7


22

SFP

Analog Out 3B -  8 to 15


23

Lookup table

eHS PWM 1 -  0 to 7


24

Config AOMR (3A,4A)

eHS PWM 2 -  8 to 15


25

RMS and Power calculation

eHS PWM 3 -  16 to 23


26


eHS PWM 4 -  24 to 31


27


eHS SWG


28


PMSM VDQ 1/2


29
PMSM VDQ 3/4

30


PMSM SH 1/2


31
Analog Out 3A -  0 to 7
32
Analog Out 3A -  8 to 15
33


34
SFP
35
Lookup Table Config
36
TSDO 10 - eHS 72 to 79
37
TSDO 11 - eHS 80 to 87
38
TSDO 12 - eHS 88 to 95
39
Analog Out 4A -  0 to 7
40
Analog Out 4A -  8 to 15

System Overview

Extensive I/O compatibility (Polymorphism)

Listed cards are compatible at the same location

Digital In/Out Mezzanine

Compatible Mezzanine Modules

OP5369


Analog In Mezzanine

Compatible Mezzanine Modules

OP5342-1 16 Ain


Analog Out Mezzanine

Compatible Mezzanine Modules

OP5330-3 16 Aout

OP5330-1 16 Aout





Permanent Magnet Synchronous Machine models (PMSM VDQ)

A total of two PMSM motors are available and configured using the Permanent Magent Synchronous Machine. The machine type could be Constant DQ, Variable DQ or BLDC. 


Schematic Editor Workflow - PMSM (VDQ - BLDC) block


Permanent Magnet Synchronous Machine Spatial Harmonics model (PMSM SH)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

A total of two PMSMSH motors are available and configured using the Permanent Magent Synchronous Machine in the Schematic Editor library.

 Schematic Editor Workflow - PMSM (SH) block


Communication port configuration for the Dual PMSM (VDQ) block

      

Dual PMSM Motors VDQ 1

Machine Label

PMSM 1

PMSM 2

Data In Port Number

28

Load In Port Number

18

Data Out Port Number

9


      

Dual PMSM Motors VDQ 2

Machine Label

PMSM 3

PMSM 4

Data In Port Number

29

Load In Port Number

19

Data Out Port Number

10

Communication port configuration for the Dual PMSM (SH) block

      

Dual PMSM Motors SH 1

Machine Label

PMSM 1

PMSM 2

Data In Port Number

30

Load In Port Number

20

Data Out Port Number

11

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module. 
Analog In - Slot 1B - Ch00-15

Encoder output

Encoder outputs are sent to 
Digital Out - Slot 2B



Encoder 1Encoder 2Encoder 3Encoder 4Encoder 5Encoder 6
ACh00Ch04Ch08Ch12Ch16Ch20
BCh01Ch05Ch09Ch13Ch17Ch21
ZCh02Ch06Ch10Ch14Ch18Ch22

SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block


Communication port configuration for the SFP mapping and communication block


SFP - Channel 0

Data In Port Number34
Load In Port Number22

Analog In module (AI)

AI block reads signals from analog input channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Power calculation module

SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.

For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock

Communication port configuration for the Power calculation block


RMS

Load In Port Number

25

Data Out Port Number

16

Analog Out module (AO)

AO block configures analog output channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Digital In module (DI)

DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Digital Out module (DO)

DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

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