Arm Current Generation Block

The Arm Current Generated block is shown in the figure below.

It is applied to form an arm current <Iarm> waveform, which is determined by the parameters shown.

When the Form of the current is set to 0: Continuous current, the arm current is kept as continuous, the current can be shown as in the following equation:

When the Form of the current is set to 1: Current with a duration, more options to trigger the pulse of the currents will be showed as the figure below,

The user has to check the boxes for specific valves to give a rising edge of currents, then arm current will output a pulse of constant magnitude for a duration of <pulse duration>seconds.

MMC Pulse Block

The MMC pulse block is shown in the figure below. It is used to manually set gating signals being sent from the CPU to FPGA.

No input and one multiplexed output port
Output has 8*6 32-bit signals, each contains 32 gating signals
Two modes for gating signal being sent to FPGA, as set in “MMC parameter” block, option “\controller\CPU gating signal mode”
Six taps “Valve(0~6)” in parameter mask with same options, each corresponding to one of 6 MMC valves
- Full mode: When the option checked, the signal for all gating signals is sent. (g1 & g2 for HB-SM, g1~g4 for FB, CD, T-SM.)
- Related mode: When option unchecked. Only g1 for HB-SM and g1 & g3 for FB, CD, T-SM are input. g2=NOT(g1), g4=NOT(g3) in HB, FB, CD-SM; g2=NOR(g1,g3), g4=g3 in T-SM.
Users can click on the ‘Help’ button and refer to the training slices to see the detailed descriptions.

MMC Parameters Block

The MMC Parameter block is shown below. It is used to set all parameters of the MMC model.

There are 5 tabs in the MMC parameters block: parameters, advanced, fault, protocol and extra.

Parameters Tab

SM type of group (1, 2, 3)	One MMC valve can have up to 3 types of SM. It sets SM type for each group. Options of SM type are: 0: Half-bridge 1: Full-bridge 2: Clamped-double 3: T-type SM
Number of SM in group (1, 2, 3)	Number of SM in group (1, 2, 3) in one valve. SMs are numbered in ascending order of groups. Total SM number should be less than or equal to the number allowed by license. Total capacitor number is ≤ 1000 in standard bitstream but can be expended at request. If one valve has only 1 or 2 SM types, SM type of group 2 or 3 can be disabled.
SM capacitance design value (farads)	Capacitance of cell capacitor in Farad.
Switch Ron (ohms)	IGBT switch ON resistance in ohm.
SM capacitor normal and fast discharge resistor design value [ohms] (e.g. [2200 200])	The resistance in parallel with the cell capacitor in normal and fast discharging mode.
Capacitor voltage base (V)	Capacitor voltage base value.
Gating signal Dead time, max 50 us, NA yet	Dead time between the upper and lower gates of one sub-module while pulse is enabled. N/A yet.

Operation Tab

Enable pulse	Enable pulse of MMC converter
G5 for CDSM	Disable: G5 is disabled Enable: G5 is enabled By protection signal: G5 is controlled by protection signal Fast discharge: when the box is checked, the shunt resistance in fast discharging mode which defined in Parameters tab will be used in the model. Vcap mode: This parameter selects how the cell capacitor voltage is calculated in the FPGA. Force bit for FBSM, usually at charging mode: force bit (g3=0, g4=1) of FBSM, usually at charging mode.
Normal Operation	For normal operation mode, where the cell capacitor voltage respects physical law, i.e. determined by the charging current and capacitance.
Vcap reset to 0	All cell capacitor voltages are forced to zero.
Vcap use average value	All capacitor voltages are calculated by the charging current and capacitance, then the average value of each arm is applied to all cell capacitors in that arm. It emulates the performance when applying an ideal capacitor voltage balancing algorithm. Not supported in current version.
Vcap reset to fixed value	All cell capacitor voltages are forced to a fixed value given in the next parameter "Vcap fix value (pu)". This mode emulates the performance when applying an ideal capacitor voltage control.
Vcap fix value (pu)	The fixed cell capacitor voltage in PU when the parameter "Vcap mode" is selected for "3: Vcap reset to fixed value". For example, in mode "3: Vcap reset to fixed value", "Vcap fixed value (PU)" is 1 PU, then all cell capacitor voltages are fixed 1 PU.
Force cap charge current to zero	This option is only for debugging mode and should not be checked for normal operation mode. When it is checked, no matter if there is arm current, the cell capacitor charging currents are forced to zero.
MMC gating signal from	Internal: gating signal from CPU or FPGA External from SFP: gating signal from SFP. If this option is selected, please follow the connections instruction in the table below and connect SFP cables in VC707.
SFP00	SFP01
SFP02	SFP03
SFP04	SFP05
SFP06	SFP07
SFP08	SFP09
SFP10	SFP11
For MMC, measurement message interval (us)	The interval that the MMC simulated in FPGA sends out the measurements through the protocol.

Controller Tab

Enable protocol port	Protocol is enabled by checking the box.
Gating signal from	Gating signal from CPU Embedded VBC in FPGA
CPU gating signal mode: related(uncheck)/full (check)	Gating signals are complimentary (g1=NOT(g2)) (check) or independent. In controller, measurement from protocol (check)/local (uncheck)
Carrier frequency (Hz), max 3000Hz, resolution 0.05Hz	PWM carrier frequency to generate IGBT gating signal in FPGA.
In controller, measurement from protocol (check)/local (uncheck)Command packet interval by controller	The interval that the controller simulated in FPGA sends out the control commands through the protocol.
Inverse current direction in protocol (positive for charging (uncheck) or discharging (check)	Inverse the current direction in protocol by checking the box.

Protection Tab

Overvoltage protection level 1 enable:	Checked: over-voltage protection is enabled, which means when the capacitor voltage is over the threshold voltage value (specified in the parameter below), the sub-module is bypassed, the capacitor voltage is latched; Unchecked: over-voltage protection is disabled.
Overvoltage threshold level 1 (pu), maximum 4 pu	When the capacitor voltage is over this value, the sub-module is bypassed, the capacitor voltage is latched, the output voltage is zero.
Overvoltage protection level 1 latch	When the Over-voltage protection option is checked, this option can be checked or not. After the sub-modules are latched when the voltage reaches the over-voltage threshold, if this option is checked, the sub-modules can be in normal working mode when their voltages are below the threshold, please check it as the initial state.
Overvoltage protection level 2 enable	It has the same meaning as level 1, 2^nd level of overvoltage protection
Overvoltage threshold level 2 (pu), maximum 4 pu	the overvoltage threshold for level 2, has the same meaning as threshold level 1.
Overvoltage protection level 2 latch	Has the same meaning as the level 1 latch.
Under-voltage protection enabled	Checked: under-voltage protection is enabled, which means when the capacitor voltage is under the threshold voltage value (specified in the parameter below), the sub-module is bypassed, the capacitor voltage is latched Unchecked: under-voltage protection is disabled.
Under-voltage threshold level (pu)	When the capacitor voltage is under this value, the sub-module is bypassed, the capacitor voltage is latched, the output voltage is zero.
Under-voltage protection latch	When the under-voltage protection option is checked, this option can be checked or not. After the sub-modules are latched when the voltage reaches the under-voltage threshold, if this option is checked, the sub-modules can be in normal working mode when their voltages are above the threshold, please check it as the initial state.

Scope Tab

Receiving packet interval(us): Instant (check)/maximum (uncheck) value	To see the MMC receiving SFP interval for instant value (check) or maximum value (uncheck).
Vcap measuring point at valve (uncheck)/control (check)	To see the Vcap from MMC or from control.
Display individual SM state	Check to see the SM state.
…on	Choose valve 0 to valve 5 to see the state.
*SM number for display (for input=n, 2n6 SM for Vcap, 2n SM for state)**	This option sets the number of SM, of which measuring info is sent to & displayed in CPU. If the value is N, Vcap of 12N SM (2N per valve) and states of 2N SM are sent.
SM selection offset (for input =x, 2x-th SM is 1^st being displayed)	This option sets which SM in a valve is the 1^st SM being displayed. For example: if in above options N=10 & x=2, Vcap of SM4~23 of valves 0~5 (120 Vcap) are sent to CPU. If further “View SM state” is checked and “View SM state on”=“valve 0”, states of SM4~23 of valves 0 are also sent to CPU.
Valve info	Showing: this option shows different debugging information comes from the valves 0: Vcap max min values: if this is selected, look at the corresponding monitoring block in the console, it displays maximum and minimum Vcap values in each valve. 1: Total SM number that: if this option is selected, another selection will show up to choose total SM number that 0: g1 is ON; 1: g2 is ON; 2: g3 is ON and 3: g4 is ON. Choose one of the options and the corresponding results will be displayed. There will also be a checkbox to choose if instant or maxmin value of it. 2: Valve state and choose the option according to the following table. When this option is selected, another option Total SM number with will be available, user then is able to choose the total SM number with different states.
SM state summary	In the FPGA model, each SM has an internal 16-bit state as below. Original SM state info of selected SM is displayed as explained in previous pages. This option displays a selected summary of SM state in a valve

bit #	SM internal state
bit 0;	G1 open circuit fault
bit 1;	G1 short circuit fault
bit 2;	G2 open circuit fault
bit 3;	G2 short circuit fault
bit 4;	G3 open circuit fault
bit 5;	G3 short circuit fault
bit 6;	G4 open circuit fault
bit 7;	G4 short circuit fault
bit 8;	breaker being closed
bit 9;	SM deactived
bit 10;	Vcap overvoltage level-1
bit 11;	Vcap overvoltage level-2
bit 12;	Vcap undervoltage
bit 13;	capacitor short circuit fault
bit 14;	reserved
bit 15;	reserved

Controller info selection

Total SM number ref output: reference received and output by the controller
1: reserved
2: reserved
3: reserved

Advanced Tab

Current sync mode (keep it as default)
Check to show advanced options (for advanced user only)	check the box to show advanced options, otherwise keep the tab as default.
FPGA clock (fixed for bitstream)	5 ns 10 ns
VEB advanced (for debugging always check)	for internal use only
FBSM works in HVDC mode	FBSM will work in HVDC mode by checking the box
Minimum number of FPGA clock per cycle	minimum number of FPGA clock per cycle is 20, keep it as default
Current sync mode (keep it as default)	eHS mode DataIn Sync mode ModelSync mode
Current correction mode	mode 0 to 6 and mode eHS, keep it as default.
Current correction default method (check)	current is corrected in default method by checking the box.
Gating signal repeated for CDSM (check)	uncheck by default
Control output: nb of SM at 1 clock	8 SM by default

CR Discrepancy Tab

Parameter discrepancy range

set range for discrepancy data. Options are

0: no discrepancy
1: max error +/-1pu; resolution 0.78%
2: max error +/-0.5pu; resolution 0.39%
3: max error +/-0.25pu; resolution 0.20%

Parameter discrepancy data

data for discrepancy patterns, a matrix variable “paradisc”. Variables “dimen_paradisc” and “depth_paradisc” are number of rows and columns of “paradisc” and set in mask of “FPGActrl” block, should not change after compilation. 3 variables are predefined in initial file MMCparameterdiscrepancy.m.

dimen_paradisc is number of patterns, ≤12;
depth_paradisc is number of discrepancy data in one pattern.

discrepancy pattern of SM Capacitance/ discharge R in valve (0~5)

to apply selected discrepancy pattern on SM C or R of valve (0~5), options are
0: no discrepancy
1~12: parameter discrepancy pattern 1~12

If pattern number> dimen_paradisc, no discrepancy applied.
If number of Cap> depth_paradisc, discrepancy applied to first depth_paradisc number of C/R; others have designed value (no discrepancy).

Fault Tab

Users can apply or clear specific faults set in “Fault” tab on selected SM set in “fault set” block.

clear temporary fault (checked)	If not checked, all SM faults will be latched. If checked, all currently non-active faults will be cleared.
set fault	drop-off list to specify if specified fault set is applied with one of the options: 0: no fault 1: fault on valve 0 only 2: identical fault on all valves 3: fault on different valves
Fault0 on Valve0	select fault 0 on valve 0 and define it in “Fault set” block
Fault1 on Valve0	select fault 1 on valve 0 and define it in “Fault set” block
Fault2 on Valve0	select fault 2 on valve 0 and define it in “Fault set” block
If select 3	fault on different valves in the option “set fault”, the same three checkboxes will display for different valves

Fault Signals in Vector

Fault signals in vector are shown below. It is used to generate a capacitor short-circuit fault signal. All switches are divided into 8 groups and 64 fault signals per group.

SM group Tab	select different SM groups with different fault pattern, users can select 3 different fault patterns. 3 SM groups have the same selections.
Selecting method	options are 1: Selection by starting # and # of SM 2: Selection 20 SM by bit set with offset 3: Select all 4: Select none Options 1 and 2 works with other parameters explained in next pages. Option 3 means all SM in valve are selected. Option 4 means no SM is selected.
[starting #, # of cell]: works with selecting method 1	selection by starting # and # of SM”. First parameter is the number of first selected SM. Second parameter is the total number of selected SM. Note first SM in a valve is numbered as SM 0. Example 1, [0 5] means that selection includes SM0 ~ SM4, total 5 SM. Example 2, [5 3] means that selection includes SM5, SM6, SM7, total 3 SM.
select 20 SM by bitset	works with selecting method 2:selection 20 SM by bit set with offset. 20 parameters with value either 1 or 0 represent 20 consecutively numbered SM being selected or not.
*offset: input N and above selection is offset by 4N**	works with selecting method 2:selection 20 SM by bit set with offset. Parameter multiplied by 4 gives offset of above selection of 20 SM.
Fault0~fault2	3 tabs to define different fault patterns
Apply (checked) or remove (unchecked) fault	If checked, fault specified in MMC parameter block will be applied to SM in selection. If unchecked, fault specified will be cleared. Of: 1: g1 fault: fault on g1 2: g2 fault: fault on g2 3: g3 fault: fault on g3 4: g4 fault: fault on g4 5: capacitor short-circuit fault: SC fault on capacitors
Open-circuit (unchecked) or short-circuit (checked) fault	when select first 4 options, this option will appear to select if the fault is open-circuit or short-circuit
On SM group 0~on SM group 2	3 options to select which fault patterns will be applied as defined in the tab “SM group”. Users can select up to 3 patterns at the same time. For example, check the box “on SM group 0” in the tab “fault 0”, the fault pattern defined in the tab “SM group à SM group 0” will be applied as “fault 0” and the valves who selected fault 0 on “MMC Parameters/fault” will have the faults.

MMC User Documentation

Functions of Input Blocks