Introduction

This block sets various parameters used by the "Modular Multilevel Converter with Integrated Controller" block.

Mask and Parameters

Parameter

SM type of group 1: Users are able to choose which type of topology of MMC sub modules in SM group 1. (Please see the figure below for the topologies).

• 0: Half-bridge: Half bridge SM topology is applied.
• 1: Full-bridge: Full bridge SM topology is applied.
• 2: Clamp-double: Clamp double SM topology is applied.
• 3: T-type : T-type SM topology is applied.

Number of SM in group 1: The number of SM in group 1. Any number equal or less than maximum number of cell supported by current version of bitstream.

SM type of group 2: Users are able to choose which type of topology of MMC sub modules in SM group 2.

• 0: Half-bridge: Half bridge SM topology is applied.
• 1: Full-bridge: Full bridge SM topology is applied.
• 2: Clamp-double: Clamp double SM topology is applied.
• 3: T-type : T-type SM topology is applied.
• 4: disabled : User can disable this group to only use group 1.

Number of SM in group 2: It has the same definition as 'Number of SM in group 1'.

SM type of group 3: It has the same definition as 'SM type of group 2'.

Number of SM in group 3: It has the same definition as 'Number of SM in group 1'.

SM capacitance design value (farads): Designed SM capacitance.

Switch Ron (Ohms): IGBT switch ON resistance in ohm. Ron*Total Number of SM should less than 256 Ohm.

SM capacitor normal and fast charge resistor design value [Ohms] (eg. [2200 200]): The resistance of the resistor in parallel with the SM capacitor in normal and fast discharge mode respectively.

Capacitor voltage base (V): The base value of SM capacitor voltage.

gating signal dead time (us), maximum 50us: Dead time between the upper and lower gates of one sub-module while pulse is enabled

Operation

Enable pulse: Pulse enable option for MMC FPGA terminal.

g5 (CDSM): Users can choose enable or disable G5 of CDSM.

• 0: diable: G5 is disabled.
• 1: enable: G5 is enabled.
• 2: by protection signal: G5 is controlled by protection signals.

Force bit for FBSM (checked to force g3=0, g4=1 as HBSM, ussually at charging mode): Force bit to make g3=0, g4=1 for FBSM.

Fast discharge: Corresponds to shunt resistances in normal and fast discharging mode, when this option is checked, use shunt resistance in fast discharge mode.

Vcap mode: Force bit to make g3=0, g4=1 for FBSM.

• 0: normal operation: In this mode the SM capacitor voltage respects physical law, i.e. determined by the charging current and capacitance.
• 1: Vcap reset to 0: In this mode all cell capacitor voltages are forced to zero.
• 2: Vcap use average value: This mode is not yet in use.
• 3: Vcap reset to fix value: In this mode all cell capacitor voltages are forced to a fixed value given in the next parameter "Vcap fix value (pu)". This mode is for debugging use.

Vcap fixed value (PU): The fixed cell capacitor voltage in PU when the parameter "Vcap mode" is selected for "3: Vcap reset to fixed value". For example, in mode "3: Vcap reset to fixed value", "Vcap fixed value (PU)" is 1 PU, then all cell capacitor voltages are fixed 1 PU.

Force cap charge current to zero: This option is only for debugging mode and should not be checked for normal operation mode. When it is checked, no matter if there is arm current, the cell capacitor charging currents are forced to zero.

MMC gating signal routing: These parameters indicate the IGBT gating signals source or location.

• 0: internal: In mode 0, gating signals are generated in the CPU and passed to the FPGA.
• 1: external from SFP: Gating signals are from external controller transmitted via SFP. If this option is selected, please follow the connections instruction in the table below and connect SFP cables in VC707.

For MMC, measurement message interval (us): The message interval of MMC measurement, in us.

Controller

Enable protocol port: Enable (checked) or disable (unchecked) the signals sending through the protocol.

Gating signal from: This parameter selects what should be the source of the gating signal sent to MMC:

• 0: Gating signals from CPU: use MMC gate signal block in console to control.
• 1: embedded VBC in FPGA: the gating signals from embedded VBC in FPGA

CPU gating signal mode: related (unchecked)/full (checked): If unchecked, the lower gating signals are automatically input as the complimentary signals of the upper gating signals (ex. if one upper gating signal is 1 then the corresponding lower gating signal is 0); if checked the lower gating signals are independent of the upper gating signals, users are able to input the gating signals independently.

In controller, measurements from protocol (check)/local (uncheck): The MMC measurements are from the protocol or local model.

Carrier frequency (Hz), max 3000 Hz, resolution 0.05 Hz: PWM carrier frequency.

Command packet inerval by controller (us): The interval that the controller simulated in FPGA sends out the control commands through the protocol.

Inverse current direction at protocol (positive for charging (unchecked) or discharging (checked)): The current direction can be reversed in protocol by checking this option.

Protection

Overvoltage protection level 1 enabled: Checked: over voltage protection level 1 is enabled, which means when the capacitor voltage is over the threshold voltage level 1 value (specified in the parameter below), the SM is bypassed, the capacitor voltage is latched; unchecked: over voltage protection level 1 is disabled

over voltage threshold level 1 (pu), maximum 4 pu: When the capacitor voltage is over this value, SM will be bypassed.

over voltage protection level 1 latch When Overvoltage protection level 1 option is checked, this option will appear in the block. After the sub-modules are latched when the voltage reach over-voltage threshold level 1, if this option is checked, the sub-modules can be in normal working mode when their voltages are blow the threshold, please check it as the initial state.

Overvoltage protection level 2 enabled: Checked: overvoltage protection level 2 is enabled, which means when the capacitor voltage is over the threshold voltage level 2 value (specified in the parameter below), the SM is bypassed, the capacitor voltage is latched; unchecked: over voltage protection level 2 is disabled

over voltage threshold level 2 (pu), maximum 4 pu: When the capacitor voltage is over this value, SM will be bypassed.

over voltage protection level 2 latch When Overvoltage protection level 2 option is checked, this option will appear in the block. After the sub-modules are latched when the voltage reach over-voltage threshold level 2, if this option is checked, the sub-modules can be in normal working mode when their voltages are blow the threshold, please check it as the initial state.

Undervoltage protection enabled: Checked: under voltage protection is enabled, which means when the capacitor voltage is under the threshold voltage value (specified in the parameter below), the SM is bypassed, the capacitor voltage is latched; unchecked: under voltage protection level 1 is disabled

Undervoltage threshold (pu): When the capacitor voltage is under this value, SM will be bypassed.

Undervoltage protection latch When undervoltage protection option is checked, this option will appear in the block. After the sub-modules are latched when the voltage reach undervoltage threshold, if this option is checked, the sub-modules can be in normal working mode when their voltages are above the threshold, please check it as the initial state.

Scope

Receiving packet interval (us): instant (checked)/ maximum (unchecked) value Monitor the receiving packet interval instant value (checked) or maximum value (unchecked).

Vcap measuring point at valve (uncheck)/control (check): to see the capacitor voltage from MMC (uncheck) or from control (check).

View SM state: check to see the SM state.

Select to view SM state on which valve: choose valve 0 to valve 5 to see the state.

SM number for display (for input=n, 2n*6 SM for Vcap, 2n SM for state): choose how many SM Vcap and states that are displayed.

SM selection offset (for input =x, SM-2x is 1st displayed): This option sets which SM in a valve is the 1st SM being displayed. For example: if in above options N=10 & x=2, Vcap of SM4~23 of valves 0~5 (120 Vcap) are sent to CPU. If further "View SM state" is checked and "View SM state on"="valve 0", states of SM4~23 of valves 0 are also sent to CPU.

SM state summary: In FPGA model, each SM has an internal 16-bit state, users can check the state bit by bit.

Valve info selection: choose to monitor valve information.

• 0: Vcap max min values: to monitor maximum and minimum values of Vcap.
• 1: Total SM number: when this option is selected, the parameter Total SM number will appear so that the option g1 is ON, g2 is ON, g3 is ON or g4 is ON must be specified, this can display the total ON gate number upon selection
• 2: SM state: to monitor the state of SM.
• 3: Reserved.

Total SM number instant value (uncheck)/max mim value (check): when the user wants to monitor the total gate number upon selection, he can choose to monitor the instant or max value by checking and unchecking the option.

Controller info selection: The information in controller.

• 0: Total inserted SM number: reference received and output by the controller.
• 1: Reserved.
• 2: Reserved.
• 3: Reserved.

Advance

Check to show advanced options (for advanced user only): Users can select the option to see advanced parameters, most users keep this whole tab by default.

Time step at CPU model (s): CPU model time step.

VBE advanced mode: For internal use. User can always check this option.

FGPA clock (fixed for bitstream): Number of FPGA clocks per cycle.

• 0: 5ns: Ts_FPGA=5ns.
• 1: 10ns: Ts_FPGA=10ns.

Minimum number of FPGA clock per cycle: minimum number of FPGA clock per cycle is 20, keep it as default.

Vmmc average over TsCPU (checked)/inst value (unchecked):MMC output voltage (Vmmc) in each valve is calculated in FPGA and passed to CPU. The CPU can either use the average Vmmc value over the last CPU time step, if this option is checked, or use the instantaneous Vmmc value at the end of last CPU time step, if not checked. Suggest to use the average value by checking this option.

VEB advanced (for debugging always check): keep it as default.

FBSM works in HVDC mode: FBSM will work in HVDC mode by checking the box.

Current sync mode:keep it as default

• 0: eHS mode.
• 1: DataIn sync mode.
• 2: ModelSync mode.

Current correction mode:keep it as default

Current correction default method (check):keep it as default

Gating signal repeated for CDSM (checked): unchecked by default.

Control output: nb of SM at 1 clock, 8 SM by default: should refer to the bitstream XSG file 

• 0: 8 SM. (for bitstream with Protocol A, e.g. VC707_2-EX-0001-3_3_1_790-MMC_m6_4T_noSFP_A-26-02.bin)
• 1: 4 SM. (for bitstream with Protocol A, e.g. VC707_2-EX-0001-3_3_1_790-MMC_m6_2T_noSFP_B-26-01.bin)
• 2: 2 SM.

CR discrepancy

parameter discrepancy range: set range for discrepancy data.

• 0: no discrepancy.
• 1: max error +/-1pu; resolution 0.78%.
• 2: max error +/-0.5pu; resolution 0.39%.
• 3: max error +/-0.5pu; resolution 0.20%.

parameter discrepancy data: data for discrepancy patterns, a matrix variable "paradisc". Variables "dimen_paradisc" and "depth_paradisc" are number of rows and columns of "paradisc" and set in mask of "FPGActrl" block, should not change after compilation. 3 variables are predefined in initial file MMCparameterdiscrepancy.m.

discrepancy pattern of SM Capacitance/ discharge R in valve (0~5): to apply selected discrepancy pattern on SM C or R of valve (0~5).

• 0: no discrepancy.
• 1~12: parameter discrepancy pattern 1 to 12. If pattern number> dimen_paradisc, no discrepancy applied. If number of Cap> depth_paradisc, discrepancy applied to first depth_paradisc number of C/R; others have designed value (no discrepancy).

Please note there is an equation regarding each ratio k in the matrix: Let's say the ratio is k, designed SM capacitance is C0 the real capacitance is Ci. We have the equation 1/Ci=(k+1)*(1/C0), therefore we have k=(C0/Ci)-1. If k>0, the real capacitance Ci is smaller than the designed C0. We have the same equation for the shunt resistance R.

Fault

This tab defines short-circuit fault applied to the capacitors of selected SM. At fault the capacitor voltage of the faulty SM will discharge to 0.Users can apply or clear specific faults set in "Fault" tab on selected SM set in "SM sel" block.

clear temporary fault (checked): If not checked, all SM faults will be latched. If checked, all currently non-active faults will be cleared.

Set fault: drop-off list to specify if specified fault set is applied with one of options

• 0: No Fault: There is no short-circuit on all of the cells.
• 1: fault on valve 0 only: The short-circuit fault is only on valve 0; when the option is selected, there are two more options appear.
• 2: identical fault on all valves: It has the same sub-modes as Mode 1, please refer to the previous statement.
• 3: fault on different valves: If the option is selected, the options of selecting faults for different 6 valves appear in which you can choose one or more out of the six arms to assign faults, the fault applications patterns are available to choose as the same in Fault on Valve 0.

Fault type: open (checked) or short circuit (unchecked) on G(1~4) Valve(0~5): to set fault type on G(1~4) of specified SM selection in Valve(0~5).

Active SM selections for fault on G(1~4) Valve(0~5): 4-element vector. i-th element =1 (i=1 to 4) means SM in i-th selection (set in "SM sel" block) is selected for fault action on G(1~4) Valve(0~5). If 2 or more selections are active, they must have same action (either apply or clear fault) set in "SM sel" block.

Active SM selections for Cap Short Circuit fault Valve(0~5): 4-element vector for SM selection to apply or clear SM capacitor short-circuit fault.

Inputs, Outputs and Signals Available for Monitoring

Inputs

This block has no input.

Outputs

The output of this block contains a composite signal of all parameters set in the parameter panel. It should be connected to the "MMC Parameters" of the "Modular Multilevel Converter with Integrated Controller" block.

Sensors

Description

Limitations

References

See Also

PWM Generation Block.