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This block enables hardware synchronization of the model where it is inserted.

NOTE: this block is also supported in XHP mode.

Depending on the Output signal waveform parameter value, the block makes use of one or two of the timers of a NI6602 card. When the waveform selected is Squarewave, the block uses counter 0 for its primary counter and counter1 for its slave counter if the counter-selected in the Counter number parameter is counter 0. If the counter selected is counter1, counter 1 becomes the primary counter and counter 0 the slave counter:

The primary counter is used to output a pulse-train, the period of which is equal to the calculation step of the model. The slave counter reads in the output signal of the primary counter and synchronizes the model on the rising edges of this signal. The only connection required is thus between OUT0 and GATE1, or between OUT1 and GATE0.

When the waveform option is set to Pulses, the block uses only one primary counter, counter 0 or counter 1 depending on the selection in the Counter number parameter. In this mode, the primary counter generates a 50ns pulse at the end of each time step:

The output signal of the primary counter can be used to synchronize acquisition of other I/O blocks, such as the OpNI6602 Event Generator block, or the OpNI6602 Event Detector block, or for triggering the acquisition of Analog Input channels (for example, see the OpNI60xE AnalogIn block), or the update of Analog Output channels (for example,see the OpNI671x Analog Out block). When the synchronization signal (output of the primary counter) is used directly at the output of the 68pin connector and is connected to multipleNI6602 Event Detector or Event Generator counters proper conditioning of the signal is required (see Characteristics section below).

The synchronization signal can also be routed to the RTSI bus for synchronization of multiple cards. The OpNI6602 Event Detector, OpNI6602 Event Generator, and OpNI671x Analog Out blocks support the option to read this signal from the RTSI bus.


BusSpecify the type of the bus (PCI or PXI) of the target computer.
PCI indexEnter the PCI index (see definition)of the card on the PCI (or PXI) bus.
Counter numberSelect the counter number, 0 or 1, for the primary counter. When the block uses two counters (see Description above), the slave counter is automatically set to counter 1 when the primary counter is counter 0, and counter 0 when the primary counter is set to counter1.
Output signal waveformSelect between Square wave or Pulses. See the Description section above for a functional description of each mode.
Route synchronization signal to RTSI busWhen this option is selected, the output of the primary counter is routed to signalRTSI0 of the RTSI bus. Note that the output signal remains also available at the 68pin connector.


This block has no inputs.


This block has no outputs.

Characteristics and Limitations

Connection Requirements

As mentioned in the functional description above, when the block outputs a square wave signal, the output pin of counter 0 or counter 1, OUT0 or OUT1, produces the reference signal. If the output signal is not routed to the RTSI bus, it must be connected to GATE1 or GATE0 (the gate pins of counter 0 and 1) at the 68pin IO connector.

Note: In this case, some conditioning of the synchronization signal is necessary to ensure the stability of the signals. For this purpose, a 7414 Schmitt Inverter should be added after OUT0 or OUT1. For more information, please contact

Connector Pin Assignments

NI6602 68-pin connector

Pin Description Number Pin Description Number 
SOURCE6 22Reserved56
Reserved 19OUT653
OUT7 16GND50
DIO7 15GND49
GND 14DIO648
DIO4 13DIO547
DIO3 12GND46
GND 11DIO245
DIO0 10DIO144
OUT1 9Reserved43
Reserved 4Reserved38
GATE0 3Reserved37
+5V 1Reserved25
Direct FeedthroughNo
Discrete sample timeNo
XHP supportYes
Work offlineNo

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