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OpNI6602 PWM Out




This block is used to produce PWM signals with the counters of the National InstrumentsNI6602 card.

The frequency and duty cycle of the signal can be modified dynamically. It is optionally possible to produce a PWM signal complementary to the original, with a specified rise-time delay between the two signals.


Bus TypeThis popup menu enables the user to select the bus type of the target computer where the NI6602 card is installed. The options are PCI or PXI
PCI IndexEnter the PCI index (see definition)of the card on the PCI (or PXI) bus.
CounterSpecify the counter (in the range 0 to 7) to be used for the PWM signal
Clock SourceTwo count sources are available: 20 MHz and 80MHz. This selection has a direct impact on the resolution of the produced signal.
Minimum frequencyThis is the minimum frequency in Hertz that can be produced by the block, which provides protection should a frequency value in the range [-INF,0+] be applied to the block. The minimum frequency that can be produced is 2*2^32 clock ticks, which can last several minutes depending on the clock source. Since a PWM cycle must be completed before a new one is issued, this protection is used to prevent losing control of the timer until such a long cycle finishes. To remove protection, set this value to 0. This parameter can also be used as the threshold for activating low-frequency protection as described in the Characteristics and Limitations section.
Complementary PWMSelect this option to enable the use of a second counter. This option requires special connections described below.
Slave counterSpecify the counter to be used for the complementary PWM signal. This parameter is available only if the Complementary PWM option is selected.
Rise-Time delaySpecify the time delay, in microseconds, that is inserted between signal1-fall and signal2-rise and also between signal2-fall a signal1-rise. The effective duty cycle in this mode is Specified duty cycle (in microseconds) - Rise Time Delay. This parameter is available only if the Complementary PWM option is selected.
Reset Counter(s) on PauseCheck this option if you need to force a reset of the counter when the model is in the Pause mode, and during the reset of the model. Without this option, counters run continuously during the pause, and are only stopped at their current level during the reset of the model. If the Complementary PWM option is selected, the reset is done on both counters selected in Counter and Slave counter parameters.


FreqSupply the desired PWM's frequency in Hz. This input can be dynamically changed during the simulation.
DutyThe duty cycle of the PWM signal expressed as a fraction of the period. For instance, a 0.25 duty cycle will produce a signal that is active one-fourth of the period. This input can be dynamically changed during the simulation.


Ack: A PWM cycle must be completed before a new set of duty cycle/frequency can be applied. The NI6602 card can have only one set of specifications in the queue, so this flag is 1 once the information set at the input of the block has been submitted to the card. If the inputs of the block did not change or if they have not yet been submitted to the card, the output is 0.

NOTE: It is always the last input that is applied to the card. Thus, if the input changes before it has been submitted to the card, the old value is lost.

Characteristics and Limitations

Output Signal Limitations

  • When using the Complementary PWM option, the minimum Rise Time Delay is equivalent to 2 clock ticks, depending on the frequency specified in ClockSource.
  • When using the Complementary PWM option, the Rise-Time Delay is always applied. Users must ensure that the Rise-Time Delay is small enough relative to the PWM period. For instance, an RTD of 10 µsnext to a 5 KHz period is disproportionate but will still be applied, and the output will be mediocre in terms of frequency and duty cycle precision, but both signals will still complement each other.
  • Users must also verify that the frequency versus duty cycle relation is within acceptable ranges, even though these are validated by the block before being submitted to the counters. For instance, at high PWM frequencies, very few clock ticks are left for controlling the duty cycle, and the relative error on both the frequency and duty cycle is therefore high. Remember that the minimum count possible for the counters is 2 clock ticks. If the complementary PWM signal is not used, the maximum possible frequency is (Count source in Hertz) / ( 2 ticks up + 2 ticks down) and the only possible duty cycle at this frequency is 0.5. Protection is still provided by the block and, if the requested count should get below 2, it is internally adjusted to this value and no efforts are made to get the closest compromise to the originally requested values.

Connection Requirements

If the Complementary PWM option is not selected, the PWM signal is directly available at the OUT pin of the specified counter.

When the Complementary PWM is selected, the OUT pin of the first counter must be connected to the GATE pin of the second counter, and the OUT pin of the second counter must be connected to the GATE pin of the first counter.

Connector Pin Assignments

Pin Description Pin Description 
1+5V 35RG 
3GATE(0) 37Reserved
4Reserved 38Reserved
5OUT(0) 39GND
8GATE(1) 42GND
9OUT(1) 43RG
10PFI_0 44PFI_1
11GND 45PFI_2
12PFI_3 46GND
13PFI_4 47PFI_5
14GND 48PFI_6
15PFI_7 49GND
16OUT(7) 50GND
17UP_DOWN(7)/AUX_LINE(7) 51GATE(7)
19RG 53OUT(6)

Producing Low-Frequency Signals

When the frequency input changes, new tick counts must be programmed in the NI6602 timers. Normally, these new values are reloaded in the timers only at the end of the period of the signal they are currently generating. This feature of the NI6602 card prevents changing rapidly the frequency when the frequency is low. In order to overcome this limitation, an algorithm is implemented in the low-level software that controls stopping and restarting the timers with new values as desired. This algorithm uses a set of User Variables detailed below.When these variables are set, the algorithm is enabled and the minimum frequency parameter is used as the threshold below which the algorithm is active.

The three following User Variables must all be defined in order to enable the low-frequency protection algorithm:

  • NI6602PWMOUT_RESET: When this variable is defined, the low-level driver automatically resets the counter if the requested frequency is below the minimum achievable frequency.
  • NI6602PWMOUT_IMMEDIATE: When this variable is defined, frequency inport values are applied as soon as they are detected by stopping and restarting the timer in order to reload new values if necessary.
  • NI6602PWMOUT_CHANGE_PROTECT: When this variable is defined, frequency changes are applied when the timer output is in the low-level. This prevents some glitches during timer restart.

Furthermore, it is possible to adjust the algorithm behavior by taking into account the time needed to stop and restart the timers. The default value for this time is set to 15 us. If the algorithm seems to produce output signals whose frequency is systematically slightly above or below the requested frequency, it is possible to define the User Variable NI6602PWMOUT_ADJUST_RESTART to modify the default time value. The value of the User Variable must be entered as an integer representing a number of microseconds. For example, settingNI6602PWMOUT_ADJUST_RESTART to 20 will make the algorithm assume that the restart time of the timers is 20 us.

Note: When using the protection algorithm, it is not recommended to set the Minimum Frequency equal to the model frequency. For example, if the model calculation step is 1ms, the Minimum Frequency should not be set to 1000Hz but to a slightly lower value like 990Hz.

Direct FeedthroughNo
Discrete sample timeNo
XHP supportYes
Work offlineNo

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