Block

Mask

Description

The Op NI6602 Event Detector block makes use of the counter/timers of the NI6602 card to read digital signals and determine when during the calculation step a transition has occurred on these input signals.

The NI6602 card holds eight 32-bit counter/timers. The block can monitor any number of these counters simultaneously, each counter having its own input signal. However, some limitations apply to counter selection and these are described in the Characteristics and Limitation section below.

Two signals must be provided to each of the counters. The standard gate input is obtained from the clock signal (such as coming from an OpSyncNI6602 block), and the secondary gate input (also known as auxiliary gate pin, or up/down pin) is connected to the digital input signal. Actual pin numbers for each counter can be found in the connector pin assignment of the 68pin connector.

The drawing below is an example of signal waveforms and returnedEvent and Time values. The raw measurement returns T measured, the time elapsed between the transition on the digital signal (the Event), and the end of the calculation step (Ts). It is then transformed in order to return Te, the time elapsed between the beginning of the time step and the occurrence of the transition on the digital signal.

All possible output values for Event and Time are presented in the outputs section below.

Synchronization with the Model Calculation Step

In order to ensure proper synchronization with the model clock, the OpNI6602 Event Detector block must be used in conjunction with the OpSync NI6602 block. The OpSync NI6602 block is a hardware synchronization block. It ensures the stability of the calculation time-step and outputs a digital signal that can be used as a time reference for other I/O blocks. Note that one or two timers(counters 0 and/or 1) of the NI6602 card are reserved for the OpSyncNI6602 block.

Depending on the options of the OpSync NI6602 block, the time reference signal is output on pin OUT0 or OUT1, the output pin of counter 0 or counter 1. The OpSync NI6602 synchronization signal can come from a different NI6602 card than the one currently in use by the Op NI6602 Event Detector block. For more information, please refer to the documentation of the OpsyncNI6602 block.

The Polarity of the Digital Input Signal

This block detects only one transition per calculation step. Detection of rising edges or falling edges can be selected in the mask. The block cannot detect rising and falling edges simultaneously. However, two blocks may be used simultaneously, each of them detecting one edge polarity. In this case, the two blocks must use different counters.

Parameters

Inputs

This block has no inputs.

Outputs

At each calculation step, the block returns two vectors of outputs containing the Event andTime values for all counters monitored by the block, in the order of the CounterList mask parameter. An example of input waveform signals and the resulting Event and Time values was presented in the functional description section above. The possible values of the Event andTime output for each counter are summarized in the following tables.

Event:

Time:

Characteristics and Limitations

Connector Pin Assignments

The table below highlights the GATE and UP_DOWN (or 2ND GATE) pins of all eight counters on the68-pin connector of the NI6602 card. For each counter monitored by the OpNI6602 Event Detector block, its GATE pin must be connected to the clock signal, and its UP_DOWN pin must be connected to the digital input signal. Remember that the GATE pins do not need to be actually connected to the synchronization signal if this signal is routed to the RTSI bus.

NI6602 68-pin connector