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OpNI6602 Event Detector




The Op NI6602 Event Detector block makes use of the counter/timers of the NI6602 card to read digital signals and determine when during the calculation step a transition has occurred on these input signals.

The NI6602 card holds eight 32-bit counter/timers. The block can monitor any number of these counters simultaneously, each counter having its own input signal. However, some limitations apply to counter selection and these are described in the Characteristics and Limitation section below.

Two signals must be provided to each of the counters. The standard gate input is obtained from the clock signal (such as coming from an OpSyncNI6602 block), and the secondary gate input (also known as auxiliary gate pin, or up/down pin) is connected to the digital input signal. Actual pin numbers for each counter can be found in the connector pin assignment of the 68pin connector.

The drawing below is an example of signal waveforms and returnedEvent and Time values. The raw measurement returns T measured, the time elapsed between the transition on the digital signal (the Event), and the end of the calculation step (Ts). It is then transformed in order to return Te, the time elapsed between the beginning of the time step and the occurrence of the transition on the digital signal.

All possible output values for Event and Time are presented in the outputs section below.

Synchronization with the Model Calculation Step

In order to ensure proper synchronization with the model clock, the OpNI6602 Event Detector block must be used in conjunction with the OpSync NI6602 block. The OpSync NI6602 block is a hardware synchronization block. It ensures the stability of the calculation time-step and outputs a digital signal that can be used as a time reference for other I/O blocks. Note that one or two timers(counters 0 and/or 1) of the NI6602 card are reserved for the OpSyncNI6602 block.

Depending on the options of the OpSync NI6602 block, the time reference signal is output on pin OUT0 or OUT1, the output pin of counter 0 or counter 1. The OpSync NI6602 synchronization signal can come from a different NI6602 card than the one currently in use by the Op NI6602 Event Detector block. For more information, please refer to the documentation of the OpsyncNI6602 block.

Note: When the Use Opsync signal from RTSI bus option is selected, the gate inputs do not need to be actually connected to the synchronization signal via the 68pin IO connector if the card that holds the Event Detector counters is connected to the card that holds the OpSync counters with an RTSI cable, or if the Event Detector and OpSync counters are located on the same NI6602 card.

The Polarity of the Digital Input Signal

This block detects only one transition per calculation step. Detection of rising edges or falling edges can be selected in the mask. The block cannot detect rising and falling edges simultaneously. However, two blocks may be used simultaneously, each of them detecting one edge polarity. In this case, the two blocks must use different counters.


Bus TypeThis popup menu enables the user to select the bus type of the target computer where the NI6602 card is installed. The options are PCI or PXI.
PCI indexEnter the PCI index (see definition)of the card on the PCI (or PXI) bus.
Counter ListEnter the vector of counter numbers that will be monitored by this block. The counters are numbered from 0 to 7, and can be entered in any order.
Clock SourceSpecifies the counting timebase of the counters. The options are 20MHz and 80MHz.
Signal Edge DetectedEnables the user to choose whether rising edges or falling edges of the signal will be taken into account by the block.
Output TypeSelect whether the time value returned by the block will be specified as a ratio of the time of the event over the duration of the step, or in seconds.
Use Opsync signal from RTSI busWhen this option is selected and when the Route synchronization signal to RTSI bus option of the OpSync NI6602 block is also selected, the connection between the GATE input pins and the synchronization signal is done internally. Otherwise, the connection must be externally done through the 68pin IO connectors.
Synchronizesee definition.


This block has no inputs.


At each calculation step, the block returns two vectors of outputs containing the Event andTime values for all counters monitored by the block, in the order of the CounterList mask parameter. An example of input waveform signals and the resulting Event and Time values was presented in the functional description section above. The possible values of the Event andTime output for each counter are summarized in the following tables.


Possibles Values Description 
1An event was detected in the previous calculation step
0No event was detected in the previous calculation step


Possible Values (ratio) Description 
0 <= x < 1 Time ratio of event occurrence over the duration of the calculation step 
1No event occurred 
Possible Values (seconds) Description 
0 <= x < Ts Time elapsed between the beginning of the calculation step and the occurrence of the event
Ts No event occurred 

Characteristics and Limitations

Connector Pin Assignments

The table below highlights the GATE and UP_DOWN (or 2ND GATE) pins of all eight counters on the68-pin connector of the NI6602 card. For each counter monitored by the OpNI6602 Event Detector block, its GATE pin must be connected to the clock signal, and its UP_DOWN pin must be connected to the digital input signal. Remember that the GATE pins do not need to be actually connected to the synchronization signal if this signal is routed to the RTSI bus.

Notes on counter selection:

  • When both the OpNI6602Event Detector and OpSync NI6602 blocks use the same NI6602card, counter 0 and/or counter 1 are reserved for the OpSync NI6602 block, and cannot be used by the OpNI6602 Event Detector block. Furthermore, in non-XHP mode, counters 2 and 3 of a NI6602 card cannot be used for Event Detection when the OpSync NI6602 block is active on that card.
  • Because of hardware stability issues with the IRQ line of counters 1 and 5, the OpNI6602Event Detector driver will prevent the user to set both counters1 and 5 of one NI6602 card in Event Detection mode.

NI6602 68-pin connector

Pin Description Number Pin Description Number 
SOURCE6 22Reserved56
Reserved 19OUT653
OUT7 16GND50
DIO7 15GND49
GND 14DIO648
DIO4 13DIO547
DIO3 12GND46
GND 11DIO245
DIO0 10DIO144
OUT1 9Reserved43
Reserved 4Reserved38
GATE0 3Reserved37
+5V 1Reserved25
Direct FeedthroughNo
Discrete sample timeNo
XHP supportYes
Work offlineNo

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