Block

Mask

Description

The OP5110-5120 OpSyncblock is an hardware synchronization block for the OP511x-OP512xfamily of boards, formerly named OPHSDIO boards.

NOTE: this block is also supported in XHP mode.

The OP5510-5120 OpSync block supports master and slave modes.In master mode, it reads in the fixed step size of the model and programs timer on the OP5510 or OP5120 card. This timer generates a synchronization signal at the end of each time step. This signal is used internally by other OP5110-5120 blocks (Event Generator, Event Detector, etc.)of the same card. This signal can also be routed out and connected to other boards for external synchronization. In slave mode, the block uses the synchronization signal produced by a master board or an external source and synchronizes its inputs and outputs with this signal.

The OP5110-5120 OpSync block also controls the selection of the output connector, internal or external, for all input and output signals. For this reason, the OP5110-5120 OpSync block must always be present in a model when other OP5110-5120 blocks are used.

Parameters

Target environment	Select between RT-LAB and xPC Target.
CardType	Select the board type in this list. Each entry of the list specifies a board number, a device ID, and when applicable, the former name of the board. The device ID of the board selected must match a board installed on the target computer otherwise an error is returned. On a Red Hat system, the device of a board is specified in the name of the bitstream programmed in this board. On a xPC Target, the device ID is obtained with the command getxpcpci all.
Board Index	Enter the board index of the card [see board index limitations in the characteristics section below]
Synchronization mode	Three modes are supported: Master, Slave or unsynchronized Slave. In master mode, the block programs an onboard timer with the sample time of the block and generates a synchronization signal each time the timer expires. This synchronization signal can be routed to one pin of the RTSI connector. In Slave mode, the board reads in a synchronization signal generated by a master board or another external source. In this mode, all features that require synchronization (Analog Input, Event Detector, EventGenerator, etc.) will fail if the synchronization signal is unplugged,and the model will freeze. In unsynchronizedSlave mode, the board programs the onboard timer with the sample time of the block, but this timer is not used for synchronizing the model. The input of the RTSI signal is disabled in this mode.

Note: these options became available with v7.2.4 + patchH, and with new versions of the bitstreams generated after this time. Before that, synchronization mode was fixed by the board index values: boards with board index =15 were master boards, boards with board index less than 15 were slave boards. If the bitstream programmed on the board is not compatible with the new options, the driver will revert to the ancient mode of operation and the new options will be disabled.

Route synchronization signal to RTSI bus	This option is available in Master mode only. Note that before v7.2.4 + patch H, the synchronization signal was always routed to pin RTSI0.
RTSI pin	Selection of the RTSI pin number. This option is available in Master mode only. Note that before v7.2.4 + patch H, the synchronization signal was always routed to pin RTSI0. Note also that Slave boards only supportRTSI0 for the input pin of the synchronization signal.
Source of the synchronization signal	This option is available in Slave mode only. It allows the user to specify if the source of the synchronization signal is a master OP5110 board or an External Source.
Sampling factor on synchronization signal	This option is available in Slave mode only. It allows the user to run models with multiple OP5110 boards with different sample times. The sampling factor must be an integer value.

Note: this parameter is disabled if the option is not supported with the selected bitstream.

Use this block forHardware Synchronization of model: This option is available inSlave mode only, and when the synchronization signal comes from an External source. When this option is checked the OP5110-5120 OpSync block is used to Hardware Synchronize the model. The sample time of the model is then controlled by the external signal, and the time factor feature of RT-LAB has no effect on the model.

Note: this parameter is disabled if the option is not supported with the selected bitstream.

IO Connectors (JP3-6:Internal,JP2:External): This popup enables the user to select the set of connectors that will be connected to the input/output signals. TheInternal connectors are the 4 40-pin onboard connectors of the PCI-boards. The External connectors are the 2 68-pin external connectors.

Sample Time (s): see definition.

Inputs

This block has no inputs.

Outputs

In slave mode, the output returns -1 when a synchronization error is detected,it returns 0 otherwise. Also in slave mode, it returns -4 when using bitstream 0x35.In master mode, it always returns 0.

Note: On xPC targets, it returns the timer's reload count and the timer's current count.

Characteristics and Limitations

Board Index Limitations

On the OP5120 boards (PC-104 format), the board index is user-selectable in the range [0-15] via a connector on the board. However, boardsOPHSDIO64 labeled v0.01 do not implement this feature, and the board index of these boards is set to the default value 15.

On the PCI boards (OP511x family), the board index is user-selectable in the range [12-15], via the jumpers JP8 on the board:

Connector Pin Assignments

OP5110-5120 boards usually ship with custom-made cables adapted to the signal conditioning required by the system they are to be connected to. Please refer to the documentation of your system for your specific connector pin assignment. If you need to prepare your own custom cable, please refer to the connector pin assignment table.

Direct Feedthrough	No
Discrete sample time	No
XHP support	Yes
Work offline	No