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OpNI60xE Analog In

Block

Mask

Description

The National InstrumentsESeries (or NI60xE) cards feature analog inputs, analog outputs, digital I/O lines and counters. This block monitors the analog input channels.

Each channel has an individually configurable mode (referenced single-ended,non-referenced single-ended and differential) and voltage range. One Op Ni60xE Analog In block supports only one mode and one voltage range for a given list of channel numbers. If the input signals require the use of several modes and voltage ranges, multiple OpNi60xE AnalogIn blocks specifying different lists of channels must be used in the RT-LAB model.

This block supports a list of PXI and PCI compatible cards. The block automatically updates the list of available voltage ranges depending on the card model selected by the user. For card specific channel number and resolution, please refer to NI documentation.

This block can also be used for hardware synchronization. Trigger source may either come from an onboard counter or from an external signal.

XHP mode is supported only when Hardware Synchronization clock and 'Use External Trigger' are both disabled.

A set of User Variables is available for this block for controlling several parameters of the acquisition. They are described in the "Characteristics and limitations" section below.

Parameters

Bus TypeSelect the bus type (PCI or PXI) of the target node.
Card TypeSelect the card model.
PCI indexEnter the PCI index (see definition)of the card on the PCI (or PXI) bus.
Voltage rangeSelect the voltage range that best fits the expected input signal range.
Channel ModeSelect the channel polarity mode in this list. Make sure that the hardware connections of the input signals are consistent with this selection.
Channel ListEnter the list of channels that will be monitored by this block. The channels can be entered in any order. If some channels require a different voltage range or channel mode than those selected above, another block must be used. Make sure that the given channel does not appear in the channel of only one blocks.
Hardware Synchronization clock

Several hardware synchronization options are available. Note that for all blocks belonging to the same IO board, all Hardware Synchronization clock parameters must be set to the same value. Sampling occurs only once for all channels.

  • Disabled: Do not use this board for hardware synchronization.
  • External Clock: The model will synchronize on an external signal fed into the trigger pin. The actual time step of the model will be determined by the period of the external signal. The model must be running in 'Hardware synchronize'mode. Note that the 'Time Factor' parameter of the MainControl panel has no meaning when the model is running in this mode. Use the Trigger Pin parameter to specify the board input to use asa trigger source. Analog inputs sampling also triggered by the signal.
  • Internal Clock: An internal timer, programmed at the given model fixed step-size will be used to synchronize the model. The model must be running in 'Hardware synchronized'mode. Analog inputs sampling also occurs when the internal timer triggers the model.
Use External TriggerSelect this option to allow an externalsignal to start the A/D conversion. The external signal should be fed into one of the available PFI pins listed in the 'Trigger pin' popup (see below). All blocks belonging to the same IO board musthave this parameter set to the same value. This parameter must bechecked if hardware synchronization clock is set to Externalclock. Also, no external trigger source may be used when hardware synchronization clock is set to Internal clock.
Trigger PinSelect the PFI pin that will be connected to theexternal trigger signal. The external GND should be connected to oneof the DGND pins. All blocks belonging to the same IO board must havethis parameter set to the same value.
Synchrosee definition.
Sample Time (s)see definition.

Inputs

This block has no inputs.

Outputs

At each calculation step of the model, the block returns the current values of the input signals connected to the card.

Only the values of the channels specified in the channel list parameters are returned and the outputs are in the order of the 'channel list' parameter. The width of the output port of the block must be equal to the number of entries in the channel list parameter. Use a demux to connect individual outputs to the rest of the model.

The values are returned in Volts.

Characteristics and Limitations

Control of the Acquisition Parameters

5 User Variables are available for this block and can be used to control and monitor the acquisition parameters. When these variables are not defined, the block reverts to its default mode, which is equivalent to the default User Variable values listed at the end if this description.

1) NI60XEAIN_OUT

This User Variable must be set to CONVERT, SAMPLE, or CONVERT_AND_SAMPLE,or OFF.

This user variable is used to view the conversion signals. When NI60XEAIN_OUTis set to CONVERT, the driver outputs a pulse on PFI7 at the beginning of each conversion. That is, if the channel list has 3 channels, 3pulses will appear for each time step.

When NI60XEAIN_OUT is set to SAMPLE, the driver outputs a pulse onPFI2 at the beginning of a series of conversion. That is, one pulse per time step will appear that represents the beginning of the acquisition.

When NI60XEAIN_OUT is set to CONVERT_AND_SAMPLE, both signals are output on PFI7 and PFI2.

2) NI60XEAIN_DELAY

This User variable must be set to ON or OFF.

This User variable allows you to add a delay between the start signal(that you can view on the PFI2 line) and the convert signal (PFI7).When the variable is set to OFF, there is no delay between the start signal and the first pulse of the convert signal. When it is set toON, the delay between the start signal and the first pulse of the convert signal is equal to the delay between two successive convert pulses..

3) NI60XEAIN_SOURCE

This User Variable must be set to one of the 4 different sources forthe Convert clock :

  • IN_TIMEBASE1: the regular timebase (20MHz),
  • IN_TIMEBASE1_DIV2: IN_TIMEBASE1 divided by 2,
  • IN_TIMEBASE2: the slow timebase (100 kHz),
  • IN_TIMEBASE2_DIV2: the slow timebase divided by 2.


4) NI60XEAIN_TICKS

This variable allows the user to change the frequency of the conversion when there are several channels in the channel list. The default value for the convert frequency is

Convert Frequency = Time Base / 20

For example, with the default timebase (20 MHz), the convert frequency is 1 MHz (1 conversion every microsecond). The User Variable NI60XEAIN_TICKSreplaces the value 20 in the Convert Frequency calculation. For example,if the User Variable NI60XEAIN_TICKS is set to 200, the Convert Frequencyis equal to TimeBase/200 = 0.1 MHz, so the conversions are less frequent. This option can be used to decrease bleeding between channels.

To reproduce the defaults (obtained when no User Variable is defined), the 5 User Variables should be set as follows:

  • NI60XEAIN_OUT to CONVERT_AND_SAMPLE,
  • NI60XEAIN_DELAY to ON,
  • NI60XEAIN_SOURCE to IN_TIMEBASE1,
  • NI60XEAIN_TICKS to 20.



Note: these options are available only when the parameter HardwareSynchronization clock is set to Disabled, or External clock.



Connector Pin Assignments

The following table gives the description of the signals related to the analog input channels and is followed by the connector pn assignments of the various NIE Series card models.

Signal Name Signal Description 
AIGND Analog Input Ground. Reference point for Referenced Single Ended mode and bias current return point for differential measurements. 
ACH<0..15> Analog Input Channels 0 to 15. Each channel pair ACH<i,i+8>(i=0..7) can be configured as either one differential input or two single-ended inputs
ACH<16..63> Analog Input Channels 16 to 63. Each channel pair ACH<i,i+8>(i=16..23, 32..39, 48..55) can be configured as either one differential input or two single-ended inputs
AISENSE Analog Input Sense. Reference point of channels 0 to 15 in Non-Referenced Single-Ended mode
AISENSE2 Analog Input Sense. Reference point of channels 16 to 63 in Non-Referenced Single-Ended mode

1) Cards NI-6070E (MIO-16E-1),NI-6052E, NI-6040E (MIO-16E-4), NI-6036E, NI-6035E, NI-6034E, NI-6033E, NI-6032E, NI-6031E, NI-6030E (MIO-16XE-10), NI-6024E,NI-6023E, NI-6011E (MIO-16XE-50):

68-pin I/O Connector Pin Assignment

Pin Description Pin Description 
34ACH8 68ACH0 
33ACH1 67AIGND 
32AIGND 66ACH9 
31ACH10 65ACH2 
30ACH3 64AIGND 
29AIGND 63ACH11 
28ACH4 62AISENSE 
27AIGND 61ACH12 
26ACH13 60ACH5 
25ACH6 59AIGND 
24AIGND 58ACH14 
23ACH15 57ACH7 
22DAC0OUT56AIGND 
21DAC1OUT55AOGND
20EXTREF54AOGND
19DIO453DGND
18DGND52DIO0
17DIO151DIO5
16DIO650DGND
15DGND49DIO2
14+5V48DIO7
13DGND47DIO3
12DGND46SCANCLK
11PFI0/TRIG145EXTSTROBE
10PFI1/TRIG2 44DGND
9DGND43PFI2/CONVERT
8+5V42PFI3/GPCTR1_SOURCE 
7DGND41PFI4/GPCTR1_GATE 
6PFI5/UPDATE 40GPCTR1_OUT
5PFI6/WFTRIG 39DGND
4DGND38PFI7/STARTSCAN
3PFI9/GPCTR0_GATE 37PFI8/GPCTR0_SOURCE 
2GPCTR0_OUT36DGND
1FREQ_OUT35DGND

2) Cards NI-6071E,NI-6033E, NI-6031E:

100-pin I/O Connector Pin Assignment

Pin Description Pin Description 
1AIGND 51ACH16 
2AIGND 52ACH24 
3ACH0 53ACH17 
4ACH8 54ACH25 
5ACH1 55ACH18 
6ACH9 56ACH26 
7ACH2 57ACH19 
8ACH10 58ACH27 
9ACH3 59ACH20 
10ACH11 60ACH28 
11ACH4 61ACH21 
12ACH12 62ACH29 
13ACH5 63ACH22 
14ACH13 64ACH30 
15ACH6 65ACH23 
16ACH14 66ACH31 
17ACH7 67ACH32 
18ACH15 68ACH40 
19AISENSE 69ACH33 
20DAC0OUT70ACH41 
21DAC1OUT71ACH34 
22EXTREF72ACH42 
23AOGND73ACH35 
24DGND74ACH43 
25DIO075AISENSE2 
26DIO476AIGND 
27DIO177ACH36 
28DIO578ACH44 
29DIO279ACH37 
30DIO680ACH45 
31DIO381ACH38 
32DIO782ACH46 
33DGND 83ACH39 
34+5V84ACH47 
35+5V85ACH48 
36SCANCLK86ACH56 
37EXTSTROBE87ACH49 
38PFIO0/TRIG188ACH57 
39PFI1/TRIG2 89ACH50 
40PFI2/CONVERT90ACH58 
41PFI3/GPCTR1_SOURCE 91ACH51 
42PFI4/GPCTR1_GATE 92ACH59 
43GPCTR1_OUT93ACH52 
44PFI5/UPDATE 94ACH60 
45PFI6/WFTRIG 95ACH53 
46PFI7/STARTSCAN96ACH61 
47PFI8/GPCTR0_SOURCE 97ACH54 
48PFI9/GPCTR0_GATE 98ACH62 
49GPCTR0_OUT99ACH55 
50FREQ_OUT100ACH63 

3) Cards NI-6025E:

100-pin I/O Connector Pin Assignment

Pin Description Pin Description 
1AIGND 51PC7 
2AIGND 52GND
3ACH0 53PC6
4ACH8 54GND
5ACH1 55PC5
6ACH9 56GND
7ACH2 57PC4
8ACH10 58GND
9ACH3 59PC3
10ACH11 60GND
11ACH4 61PC2
12ACH12 62GND
13ACH5 63PC1
14ACH13 64GND
15ACH6 65PC0
16ACH14 66GND
17ACH7 67PB7
18ACH15 68GND
19AISENSE 69PB6
20DAC0OUT70GND
21DAC1OUT71PB5
22RESERVED72GND
23AOGND73PB4
24DGND74GND
25DIO075PB3
26DIO476GND
27DIO177PB2
28DIO578GND
29DIO279PB1
30DIO680GND
31DIO381PB0
32DIO782GND
33DGND 83PA7
34+5V84GND
35+5V85PA6
36SCANCLK86GND
37EXTSTROBE87PA5
38PFI0/TRIG188GND
39PFI1/TRIG2 89PA4
40PFI2/CONVERT90GND
41PFI3/GPCTR1_SOURCE 91PA3
42PFI4/GPCTR1_GATE 92GND
43GPCTR1_OUT93PA2
44PFI5/UPDATE 94GND
45PFI6/WFTRIG 95PA1
46PFI7/STARTSCAN96GND
47PFI8/GPCTR0_SOURCE 97PA0
48PFI9/GPCTR0_GATE 98GND
49GPCTR0_OUT99+5V
50FREQ_OUT100GND
Direct FeedthroughNo
Discrete sample timeNo
XHP supportsee Description
Work offlineNo

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