Library

RTE-Drive Power Electronics

Block

Note: This TSB is now obsolete. It is now replaced by a new TSB block with high-impedance capability located in ARTEMiS (in ARTEMiS > Tools > Custom Models > TSB)

Description

The RTE-Drive 2-Level Time Stamped Bridge (TSB) block implements a 2-level bridge. The bridge models IGBT/GTO/MOSFET devices controlled by ideal switch with their anti-parallel diode. The following figure presents the equivalent electrical circuit of one phase of the RTE-Drive TSB 2- Level block.

Note: The model is only available for 3-phase output. If fewer phases are required, the user can leave the unused phases open.

The working principle of the model is one of the average models. In the normal continuous conduction mode, the output voltage of each phase is set equal to either V+ or V- input voltage multiplied by the conduction time of the gate signal at each time step.

When no pulses are present for BOTH IGBT, the output of the model is set in high-impedance mode at the next current zero-crossing.

In this high-impedance mode, if the load voltage becomes higher/lower than the DC-link voltages, the model enters into rectification mode, that is it will simulate the effect of the anti-parallel diodes.

Mask

RTE-Drive 2-Level TSB HighZ Rect Mask

Parameters

Number of bridge arms	Currently set to 3.
Ron (ohms) Forward Voltage (V)	Internal resistance and forward voltage drop of either IGBT or anti-parallel devices, in Ohms or V.
High impedance in non-conducting state(Ohms)	This is the value of the output impedance of the inverter output when it enters the high impedance mode. This value cannot be made arbitrarily high because of numerical stability concerns.
Nominal DC link voltage	This value is required for the calculation of the DC-link input current. When the input voltage is at least 25% of the nominal voltage, the input current is computed with power balance (VabcIabc=VdcIdc). Below 25%, the input current is computed from load currents multiplied by IGBT conduction times.
Disable natural rectification mode	Disable the internal algorithm that enables the natural rectification by anti-parallel diodes. This may be useful to optimize real-time performances.
Disable DC-link current calculations	Disable the internal algorithm that computes the DC-link currents. This may be useful to optimize real-time performances.

Inputs and Outputs signals

g (RTE) (size 6)	RT-EVENTS signals that control the switch gates.
V + (SPS)	Positive DC-link SimPowerSystems connection.
V- (SPS)	Negative DC-link SimPowerSystems connection.
OpenPhase (size 3)	When set to 1, creates an open-circuit fault at the output of the phase of the inverter.
A,B,C (SPS)	Inverter output connection points (phases A, B and C) for SimPowerSystems.
sw (size 3)	This signal indicates that the inverter phase is open when equal to one. The signal can be used to compensate for the non-infinite high-impedance value by forcing load current to zero for example.
Vabc_inv (size 3)	Voltage measurement of the middle point of the inverter. This value is normally equal to the inverter output voltage value except when OpenPhase is set to 1. In that case, this signal is the voltage in front of the open phase fault.

Characteristics

Direct Feedthrough	No
Sample Time	Inherited and fixed discrete.
Work offline	Yes
Dimensionalized	No

Limitations

Fault insertion

The RTE-Drive 2-Level TSB Block internal model allows certain faults to be made with it. In all cases, the fault impedance can be limited by numerical stability issues because of the RTE-Drive 2-Level TSB Block introduces a delay between the input and the output of the model.

Fault type
AC-side open phase	Supported. Made internally in SPS. The ’Open_phase’ input of the block controls this type of fault.
AC-side short-circuit	Supported. Made internally in SPS.
Open DC-link input	Not supported.
DC-link short circuit	Supported. Made internally in SPS.
Internal IGBT open-phase fault	Supported through IGBT gating signal.
Internal IGBT short-circuit.	Not supported.
Diode open-circuit/short-circuit	Not supported.

Example

N/A.

RT-LAB Documentation

RTE-Drive 2-Level TSB with High-Impedance and Rectification Modes