Library

RTE-Drive Power Electronics

Block

Description

The RTE-Drive 2-Level Time Stamped Bridge (TSB) block implements a 2-level (2-switch) bridge for which the gates are controlled by RTE Boolean signals. The number of arms in parallel can be selected from 1 to 3. The bridge models IGBT/GTO/MOSFET devices controlled by an ideal switch with their anti-parallel diode. The following figure presents the equivalent electrical circuit of the RTE-Drive TSB 2- Level block.

The switch model is simulated as a resistor Ron and a DC voltage source Vf, connected in series with a switch. The switch is controlled by the gate signal g.

When the upper switch or upper anti-parallel diode conducts, the V_abc output equals the V_dc input (minus internal voltage drops). When the lower switch or diode of the leg conducts, the V_abc output is equal to 0 (plus internal voltage drops). This load, that has a voltage-input current-output causality (like an inductance), outputs a current which in fed to the I_abc input.

The I_dc output is computed from all the upper switches or diodes conduction times.

Mask

Parameters

Input

The following table presents the input signals of the block when the voltage output data type parameter is Simulink.

The following table presents the input signals of the block when the voltage output data type parameter is SimPowerSystems.

Output

The following table presents the input signals of the block when the voltage output data type parameter is Simulink.

The following table presents the input signals of the block when the voltage output data type parameter is SimPowerSystems.

Characteristics

Limitations

Absence of switch gate signals

The block is not accurate when simulating the effect of completely shutting off all IGBT gate pulses, like in emergency shutdown for example. This has the effect of letting the anti-parallel diode turn on/off naturally, a case for which the Time-Stamped Bridge is not designed.

Input to output delay

Since RT-EVENTS version 3.3.x, optimizations in Time-Stamp Bridges have been made to reduce the input to output delay due to Simulink-SPS interfacing. This optimization does concern the TSB when the Output Data Type parameter is SimPowerSystems.

Because the Time-Stamp Bridge has a switching function for which the outputs are directly dependant on the inputs, algebraic loops need to be broken when connecting it in the SimPowerSystems mode, which is obtained through forcing single time-step delays at the input(s) or the output(s) of the model. The optimization implies the displacement of the simulation delays from the output AC voltage(s) and DC current(s) to the input DC voltage(s) and AC current. This modification allows for better simulation of a strong majority of applications where a constant voltage is found on the DC bus(ses) (or the time constant of the DC voltage is small compared to the time step), due to a fixed voltage source or control actions.

Example

The following figures present a simple 2-level chopper circuit and its Simulink implementation. Refer to the rte_2level_chopper.mdl example file. The IGBT is driven at a fixed frequency of 10kHz and the simulation time step is 10 μs. The upper part of the Simulink model is the time-stamped bridge implementation of the chopper while the bottom part is the SimPowerSystem implementation.

With those parameters, the duty cycle of the chopper has been scanned, that is the ratio of the upper IGBT conduction time by the chopper frequency. The following figure shows the result of scanning the duty-cycle of the chopper for the time-stamping technique vs. SimPowerSystem block set technique. While both techniques have the same response at 0.1 μs simulation time step, they differ a lot at 10 μs: Simscape Power Systems exhibits strong non-linearity (red curve) while the time-stamped bridge model is still linear (blue curve). The time-stamped bridge is as precise as reference simulations made at 0.1 μs.