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OpNI60xE Analog In
Block
Mask
Description
The National InstrumentsESeries (or NI60xE) cards feature analog inputs, analog outputs, digital I/O lines and counters. This block monitors the analog input channels.
Each channel has an individually configurable mode (referenced single-ended,non-referenced single-ended and differential) and voltage range. One Op Ni60xE Analog In block supports only one mode and one voltage range for a given list of channel numbers. If the input signals require the use of several modes and voltage ranges, multiple OpNi60xE AnalogIn blocks specifying different lists of channels must be used in the RT-LAB model.
This block supports a list of PXI and PCI compatible cards. The block automatically updates the list of available voltage ranges depending on the card model selected by the user. For card specific channel number and resolution, please refer to NI documentation.
This block can also be used for hardware synchronization. Trigger source may either come from an onboard counter or from an external signal.
XHP mode is supported only when Hardware Synchronization clock and 'Use External Trigger' are both disabled.
A set of User Variables is available for this block for controlling several parameters of the acquisition. They are described in the "Characteristics and limitations" section below.
Parameters
Bus Type | Select the bus type (PCI or PXI) of the target node. |
---|---|
Card Type | Select the card model. |
PCI index | Enter the PCI index (see definition)of the card on the PCI (or PXI) bus. |
Voltage range | Select the voltage range that best fits the expected input signal range. |
Channel Mode | Select the channel polarity mode in this list. Make sure that the hardware connections of the input signals are consistent with this selection. |
Channel List | Enter the list of channels that will be monitored by this block. The channels can be entered in any order. If some channels require a different voltage range or channel mode than those selected above, another block must be used. Make sure that the given channel does not appear in the channel of only one blocks. |
Hardware Synchronization clock | Several hardware synchronization options are available. Note that for all blocks belonging to the same IO board, all Hardware Synchronization clock parameters must be set to the same value. Sampling occurs only once for all channels.
|
Use External Trigger | Select this option to allow an externalsignal to start the A/D conversion. The external signal should be fed into one of the available PFI pins listed in the 'Trigger pin' popup (see below). All blocks belonging to the same IO board musthave this parameter set to the same value. This parameter must bechecked if hardware synchronization clock is set to Externalclock. Also, no external trigger source may be used when hardware synchronization clock is set to Internal clock. |
Trigger Pin | Select the PFI pin that will be connected to theexternal trigger signal. The external GND should be connected to oneof the DGND pins. All blocks belonging to the same IO board must havethis parameter set to the same value. |
Synchro | see definition. |
Sample Time (s) | see definition. |
Inputs
This block has no inputs.
Outputs
At each calculation step of the model, the block returns the current values of the input signals connected to the card.
Only the values of the channels specified in the channel list parameters are returned and the outputs are in the order of the 'channel list' parameter. The width of the output port of the block must be equal to the number of entries in the channel list parameter. Use a demux to connect individual outputs to the rest of the model.
The values are returned in Volts.
Characteristics and Limitations
Control of the Acquisition Parameters
5 User Variables are available for this block and can be used to control and monitor the acquisition parameters. When these variables are not defined, the block reverts to its default mode, which is equivalent to the default User Variable values listed at the end if this description.
1) NI60XEAIN_OUT
This User Variable must be set to CONVERT, SAMPLE, or CONVERT_AND_SAMPLE,or OFF.
This user variable is used to view the conversion signals. When NI60XEAIN_OUTis set to CONVERT, the driver outputs a pulse on PFI7 at the beginning of each conversion. That is, if the channel list has 3 channels, 3pulses will appear for each time step.
When NI60XEAIN_OUT is set to SAMPLE, the driver outputs a pulse onPFI2 at the beginning of a series of conversion. That is, one pulse per time step will appear that represents the beginning of the acquisition.
When NI60XEAIN_OUT is set to CONVERT_AND_SAMPLE, both signals are output on PFI7 and PFI2.
2) NI60XEAIN_DELAY
This User variable must be set to ON or OFF.
This User variable allows you to add a delay between the start signal(that you can view on the PFI2 line) and the convert signal (PFI7).When the variable is set to OFF, there is no delay between the start signal and the first pulse of the convert signal. When it is set toON, the delay between the start signal and the first pulse of the convert signal is equal to the delay between two successive convert pulses..
3) NI60XEAIN_SOURCE
This User Variable must be set to one of the 4 different sources forthe Convert clock :
- IN_TIMEBASE1: the regular timebase (20MHz),
- IN_TIMEBASE1_DIV2: IN_TIMEBASE1 divided by 2,
- IN_TIMEBASE2: the slow timebase (100 kHz),
- IN_TIMEBASE2_DIV2: the slow timebase divided by 2.
4) NI60XEAIN_TICKS
This variable allows the user to change the frequency of the conversion when there are several channels in the channel list. The default value for the convert frequency is
Convert Frequency = Time Base / 20
For example, with the default timebase (20 MHz), the convert frequency is 1 MHz (1 conversion every microsecond). The User Variable NI60XEAIN_TICKSreplaces the value 20 in the Convert Frequency calculation. For example,if the User Variable NI60XEAIN_TICKS is set to 200, the Convert Frequencyis equal to TimeBase/200 = 0.1 MHz, so the conversions are less frequent. This option can be used to decrease bleeding between channels.
To reproduce the defaults (obtained when no User Variable is defined), the 5 User Variables should be set as follows:
- NI60XEAIN_OUT to CONVERT_AND_SAMPLE,
- NI60XEAIN_DELAY to ON,
- NI60XEAIN_SOURCE to IN_TIMEBASE1,
- NI60XEAIN_TICKS to 20.
Note: these options are available only when the parameter HardwareSynchronization clock is set to Disabled, or External clock.
Connector Pin Assignments
The following table gives the description of the signals related to the analog input channels and is followed by the connector pn assignments of the various NIE Series card models.
Signal Name | Signal Description |
---|---|
AIGND | Analog Input Ground. Reference point for Referenced Single Ended mode and bias current return point for differential measurements. |
ACH<0..15> | Analog Input Channels 0 to 15. Each channel pair ACH<i,i+8>(i=0..7) can be configured as either one differential input or two single-ended inputs |
ACH<16..63> | Analog Input Channels 16 to 63. Each channel pair ACH<i,i+8>(i=16..23, 32..39, 48..55) can be configured as either one differential input or two single-ended inputs |
AISENSE | Analog Input Sense. Reference point of channels 0 to 15 in Non-Referenced Single-Ended mode |
AISENSE2 | Analog Input Sense. Reference point of channels 16 to 63 in Non-Referenced Single-Ended mode |
1) Cards NI-6070E (MIO-16E-1),NI-6052E, NI-6040E (MIO-16E-4), NI-6036E, NI-6035E, NI-6034E, NI-6033E, NI-6032E, NI-6031E, NI-6030E (MIO-16XE-10), NI-6024E,NI-6023E, NI-6011E (MIO-16XE-50):
68-pin I/O Connector Pin Assignment
Pin | Description | Pin | Description |
---|---|---|---|
34 | ACH8 | 68 | ACH0 |
33 | ACH1 | 67 | AIGND |
32 | AIGND | 66 | ACH9 |
31 | ACH10 | 65 | ACH2 |
30 | ACH3 | 64 | AIGND |
29 | AIGND | 63 | ACH11 |
28 | ACH4 | 62 | AISENSE |
27 | AIGND | 61 | ACH12 |
26 | ACH13 | 60 | ACH5 |
25 | ACH6 | 59 | AIGND |
24 | AIGND | 58 | ACH14 |
23 | ACH15 | 57 | ACH7 |
22 | DAC0OUT | 56 | AIGND |
21 | DAC1OUT | 55 | AOGND |
20 | EXTREF | 54 | AOGND |
19 | DIO4 | 53 | DGND |
18 | DGND | 52 | DIO0 |
17 | DIO1 | 51 | DIO5 |
16 | DIO6 | 50 | DGND |
15 | DGND | 49 | DIO2 |
14 | +5V | 48 | DIO7 |
13 | DGND | 47 | DIO3 |
12 | DGND | 46 | SCANCLK |
11 | PFI0/TRIG1 | 45 | EXTSTROBE |
10 | PFI1/TRIG2 | 44 | DGND |
9 | DGND | 43 | PFI2/CONVERT |
8 | +5V | 42 | PFI3/GPCTR1_SOURCE |
7 | DGND | 41 | PFI4/GPCTR1_GATE |
6 | PFI5/UPDATE | 40 | GPCTR1_OUT |
5 | PFI6/WFTRIG | 39 | DGND |
4 | DGND | 38 | PFI7/STARTSCAN |
3 | PFI9/GPCTR0_GATE | 37 | PFI8/GPCTR0_SOURCE |
2 | GPCTR0_OUT | 36 | DGND |
1 | FREQ_OUT | 35 | DGND |
2) Cards NI-6071E,NI-6033E, NI-6031E:
100-pin I/O Connector Pin Assignment
Pin | Description | Pin | Description |
---|---|---|---|
1 | AIGND | 51 | ACH16 |
2 | AIGND | 52 | ACH24 |
3 | ACH0 | 53 | ACH17 |
4 | ACH8 | 54 | ACH25 |
5 | ACH1 | 55 | ACH18 |
6 | ACH9 | 56 | ACH26 |
7 | ACH2 | 57 | ACH19 |
8 | ACH10 | 58 | ACH27 |
9 | ACH3 | 59 | ACH20 |
10 | ACH11 | 60 | ACH28 |
11 | ACH4 | 61 | ACH21 |
12 | ACH12 | 62 | ACH29 |
13 | ACH5 | 63 | ACH22 |
14 | ACH13 | 64 | ACH30 |
15 | ACH6 | 65 | ACH23 |
16 | ACH14 | 66 | ACH31 |
17 | ACH7 | 67 | ACH32 |
18 | ACH15 | 68 | ACH40 |
19 | AISENSE | 69 | ACH33 |
20 | DAC0OUT | 70 | ACH41 |
21 | DAC1OUT | 71 | ACH34 |
22 | EXTREF | 72 | ACH42 |
23 | AOGND | 73 | ACH35 |
24 | DGND | 74 | ACH43 |
25 | DIO0 | 75 | AISENSE2 |
26 | DIO4 | 76 | AIGND |
27 | DIO1 | 77 | ACH36 |
28 | DIO5 | 78 | ACH44 |
29 | DIO2 | 79 | ACH37 |
30 | DIO6 | 80 | ACH45 |
31 | DIO3 | 81 | ACH38 |
32 | DIO7 | 82 | ACH46 |
33 | DGND | 83 | ACH39 |
34 | +5V | 84 | ACH47 |
35 | +5V | 85 | ACH48 |
36 | SCANCLK | 86 | ACH56 |
37 | EXTSTROBE | 87 | ACH49 |
38 | PFIO0/TRIG1 | 88 | ACH57 |
39 | PFI1/TRIG2 | 89 | ACH50 |
40 | PFI2/CONVERT | 90 | ACH58 |
41 | PFI3/GPCTR1_SOURCE | 91 | ACH51 |
42 | PFI4/GPCTR1_GATE | 92 | ACH59 |
43 | GPCTR1_OUT | 93 | ACH52 |
44 | PFI5/UPDATE | 94 | ACH60 |
45 | PFI6/WFTRIG | 95 | ACH53 |
46 | PFI7/STARTSCAN | 96 | ACH61 |
47 | PFI8/GPCTR0_SOURCE | 97 | ACH54 |
48 | PFI9/GPCTR0_GATE | 98 | ACH62 |
49 | GPCTR0_OUT | 99 | ACH55 |
50 | FREQ_OUT | 100 | ACH63 |
3) Cards NI-6025E:
100-pin I/O Connector Pin Assignment
Pin | Description | Pin | Description |
---|---|---|---|
1 | AIGND | 51 | PC7 |
2 | AIGND | 52 | GND |
3 | ACH0 | 53 | PC6 |
4 | ACH8 | 54 | GND |
5 | ACH1 | 55 | PC5 |
6 | ACH9 | 56 | GND |
7 | ACH2 | 57 | PC4 |
8 | ACH10 | 58 | GND |
9 | ACH3 | 59 | PC3 |
10 | ACH11 | 60 | GND |
11 | ACH4 | 61 | PC2 |
12 | ACH12 | 62 | GND |
13 | ACH5 | 63 | PC1 |
14 | ACH13 | 64 | GND |
15 | ACH6 | 65 | PC0 |
16 | ACH14 | 66 | GND |
17 | ACH7 | 67 | PB7 |
18 | ACH15 | 68 | GND |
19 | AISENSE | 69 | PB6 |
20 | DAC0OUT | 70 | GND |
21 | DAC1OUT | 71 | PB5 |
22 | RESERVED | 72 | GND |
23 | AOGND | 73 | PB4 |
24 | DGND | 74 | GND |
25 | DIO0 | 75 | PB3 |
26 | DIO4 | 76 | GND |
27 | DIO1 | 77 | PB2 |
28 | DIO5 | 78 | GND |
29 | DIO2 | 79 | PB1 |
30 | DIO6 | 80 | GND |
31 | DIO3 | 81 | PB0 |
32 | DIO7 | 82 | GND |
33 | DGND | 83 | PA7 |
34 | +5V | 84 | GND |
35 | +5V | 85 | PA6 |
36 | SCANCLK | 86 | GND |
37 | EXTSTROBE | 87 | PA5 |
38 | PFI0/TRIG1 | 88 | GND |
39 | PFI1/TRIG2 | 89 | PA4 |
40 | PFI2/CONVERT | 90 | GND |
41 | PFI3/GPCTR1_SOURCE | 91 | PA3 |
42 | PFI4/GPCTR1_GATE | 92 | GND |
43 | GPCTR1_OUT | 93 | PA2 |
44 | PFI5/UPDATE | 94 | GND |
45 | PFI6/WFTRIG | 95 | PA1 |
46 | PFI7/STARTSCAN | 96 | GND |
47 | PFI8/GPCTR0_SOURCE | 97 | PA0 |
48 | PFI9/GPCTR0_GATE | 98 | GND |
49 | GPCTR0_OUT | 99 | +5V |
50 | FREQ_OUT | 100 | GND |
Direct Feedthrough | No |
---|---|
Discrete sample time | No |
XHP support | see Description |
Work offline | No |
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