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HYPERSIM

Software Toolboxes Installed with HYPERSIM

Toolbox

Version Number

eFPGASIM (FPGA-Based Simulation)

2.20.1

New features

Improvements

  • Prevent the creation of an I/O Interface with a duplicated name.

  • It is now possible to start/stop the recording of signals directly in the /wiki/spaces/DOCHS/pages/20176638.

    • Note that the control center has to be launched before the simulation has started.

  • Error highlight in HYPERSIM console has been improved.

  • An error message is now displayed when the network adapter of the localhost target is set to an invalid IP address in the Target Manager.

    • Note that before that, the HYPERSIM engine would simply crash.

  • The Target Managerlicense panel now warns when no license is installed.

  • The Load Flow Viewer now has a “clear all” contextual menu to clear the content of the “Output” tab.

  • Firmware and Hardware mismatches are now clearly stated in the simout console.

Bug fixes

  • Fixed an issue where the RT Monitor table was displaying incorrect status in the “Enabled” column when scrolling the table

  • Fixed the Start/stop timeout defined in HYPERSIM (Simulation Settings → Advanced → Simulation Server) that was not always correctly taken into account.

  • Fixed an issue during analyse when a UCM with selected sensors was duplicated.

  • Fixed an issue where the Activation Tool was not responding when applying a license from Help&Support.

  • Fixed an issue where the HYPERSIM engine was crashing when analyzing the network from the Load Flow Viewer.

  • Fixed an issue where the HYPERSIM engine would crash with certain parameter configuration of the 3-winding, w/sat + tap +dec block. The engine would crash when

    • the Vmin parameter was greater than the Vmax parameter, or

    • the Vnom parameter was not between Vmax and Vmin

  • Fixed a HYPERSIM engine crash when a file that is not a .pun was used in line components.

  • Fixed an issue that was slowing down the load flow computation in some cases.

  • Fixed a bug where Load Flow properties weren't being saved when the model was saved.

  • Fixed an issue where the Frequency Protection block was not taking into account the initial value.

  • Fixed an issue where changes to parameters in the Load Flow window were not applied, despite appearing to update visually.

  • Fixed an issue where Line with Line generator did not take the frequency and the ground resistivity into consideration.

Removed

Signal Visualization and Processing

Dashboards

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FPGAScope

  • Signal display order in the FPGA Scope now follows the order defined in the FSD file.

  • Fixed potential ScopeView crash when making an FPGA Scope acquisition with multiple FPGAs

Unified Database

PowerFactory Import

PSS/E Import

  • The following components are now imported as native HYPERSIM components

    • IEESGO

    • GGOV1

    • DEGOV

    • IEEEG1

    • ESAC6A

  • Added warning message when a model is imported without a dyr file

  • Improved import time performance for large models

  • Fixed an error in connecting the ESST1A

PSCAD Import

  • Fixed an issue when several master:import shared the same name in a given subsystem

  • Fixed missing items in the PSCAD input model intermediate library

I/O Interfaces

  • Allow signals to be renamed in the I/O Interface Configuration window

  • Improved stability by ensuring that asynchronous computation components of I/O interfaces run either on core 0 or on a dedicated core, but not on the core of the simulation itself

CAN

  • Added support for the CAN driver using the Kvaser PCIe card

FPGAScope

  • Fixed capability to differentiate boards of the same family type

  • Fixed crash of simulation when using an RT core

IEC 61850

  • Added support for sending a report to multiple MMS client instances

MODBUS Slave

  • Added support for TCP slave IDs up to 255

OPAL-RT Board

  • Added capability to program multiple OP4810-IO/OP4815-IO platforms in parallel during the load of a model

  • Added the display of extra information such as the IP and MAC addresses to the detection of OP4810-IO/OP4815-IO platforms

  • Improved workflow by keeping connections even if a raw data point's name changes

  • Improved workflow by skipping bitstream programming if OP4810-IO/OP4815-IO platforms are configured with an empty chassis name and/or an empty IP address

  • Fixed reload of bitstreams on SGI systems

  • Fixed bitstream configuration update mechanism to:

    • keep the name of raw data signals

    • keep the byte and bit offsets of raw data signals

    • keep the state of the ‘Enable FPGA scope’ check-box

    • support merging configurations for OP48H20 cards

  • Fixed filter for bitstream file browser

  • Fixed wrongly displayed message about firmware mismatch

  • Fixed wrongly found hardware mismatch for extra slot of OP4810-IO/OP4815-IO platforms

  • Fixed validation of threshold limits for digital channels

Synchronization

  • Fixed logs that were referencing the wrong network interface used by the Oregano card

FPGA-Based Power Electronics Toolbox

eHS Blockset

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