The FPGA Scope enables the monitoring of high-speed signals internal to an FPGA board connected to an OPAL-RT Simulator, acquired directly on FPGA at a rate faster than the simulation step.

The feature relates to the low-level acquisition system, and when the feature is enabled, data is made available to the user for visualization through the ScopeView interface or the DataLogger APIs.

Step 1: Feature Availability

The feature is available in all OPAL-RT firmware provided as an OPBIN file, for FPGA cards connected to the simulation through a PCI-express interface. It is enabled through the option “Enable FPGA Scope” in the OPAL-RT Board I/O configuration.

To access the option, select the I/O interface button from the Sensors & I/Os section of the main HYPERSIM ribbon.

Open

Then select the “Enable FPGA Scope” option in the OPAL-RT Board I/O configuration.

Open

Typically, all simulator input/output signals are available for visualization through the FPGA Scope. Additionally, if present, FPGA-based controllers and solvers such as eHS, or custom probes on other functionalities, can provide signals to the FPGA Scope.

Step 2: Configuring the target

As mentioned in the network section of HYPERSIM Target Manager, the target network interface needs to be selected manually (using the fixed, range or network interface mode).

Step 3: Visualizing the signals

From the time the simulation is executed, the signals acquired by the FPGA Scope can be visualized in ScopeView following this procedure:

1. From HYPERSIM, open ScopeView (see HYPERSIM Ribbon Options)
   
   
   

2. In ScopeView, load the Data Source by selecting the simulator IP address into the "Target" field of the FPGA Scope tab, then click the refresh button. Once selected, press "Load".
   
   
   

    

3. In the signal selection interface, select the signals to be visualized.

4. In the ScopeView oscilloscope interface, configure the trigger if required. Adjust the acquisition period and window size, trigger characteristics, and then run an acquisition by clicking the black "Start" button.
   
   

Additional Information

Acquisition Period

The minimal acquisition period depends on the number of signals selected for acquisition. As a rule of thumb, the minimal acquisition period in FPGA clock cycles is equal to the number of signals selected, plus one. This means that considering a 200 MHz FPGA clock, the minimal acquisition period is 10 nanoseconds for one signal selected, 15 ns for two signals, 20 ns for three signals, etc.

One notable exception to that is that in some cases, more than one signal can be acquired simultaneously. As an example, all 32 signals coming from a digital input conditioning module are in general acquired simultaneously, and count for only one signal in the computation of the minimal acquisition period.

Acquisition Window Time Length

The RAM memory that can be allocated to the data recovery is limited to 4 MB, limiting the maximum length of the acquisition window.

The maximum acquisition window length in seconds is inversely proportional to the number of signals selected and proportional to the acquisition period.

By default, when the FPGA Scope source is loaded in ScopeView, the window length is set to its maximum length for the signals selected and the default acquisition period. The window length must be manually shortened if the acquisition period is decreased. The window can be lengthened if the acquisition period is increased.