Documentation Home Page ◇ eHS Toolbox Home Page
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

V2.13 Official Firmware Documentation

Owned by Fabien Ducat
Last updated: Aug 14, 2023
4 min read

Software Requirements

General Firmware list

Legend

Status

SE Available in Schematic Editor Workflow

SPS Available in Simscape Electrical Specialized Power Systems (SPS) Workflow

SE* Custom Schematic Editor Workflow

* Custom firmware descriptions allow external models to be integrated into the Schematic Editor S-function Workflow.

 

Important note

Extra costs might apply for custom and non-standard firmware.

OP57XX - OP56XX

OP57XX - OP56XX

Part Number

Details

Version

Generation
Workflow*

eHS licence class

Machines

Miscellaneous Features

Quad Encoder Resolver

Bitstream
Source File

FW300-V71

Virtex-7 VC707 - eHS

1.10.0

Gen4

SE

SPS

x128

x64

x32

  • 4x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

VC707_2-EX-0001-3_3_4_807-eHSx128_Gen4_Machines_IOConfig1-35-49

OP5607_300_eHS_Gen4_x128_Machines_SE_withIOs_rtxsg

FW300-V71

Virtex-7 VC707 - eHS

1.3.0

Gen4

SE

SPS

x128

x64

x32

  • 4x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM with Saturation

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

VC707_2-EX-0001-3_3_4_807-eHSx128_Gen4_Induction_Machines_IOConfig1-40-18

OP5607_300_eHS_Gen4_x128_Induction_Machines_SE_withIOs_rtxsg

FW301-V71

Virtex-7 VC707 - eHS

1.8.0

Gen4

SE

SPS

x128

x64

x32

  • 4x PMSM Spatial Harmonics

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

VC707_2-EX-0001-3_3_4_807-eHSx128_Gen4_PMSMSH_IOConfig1-03-16

OP5607_300_eHS_Gen4_x128_PMSMSH_SE_withIOs_rtxsg

 

Virtex-7 VC707 - eHS

1.3.2

Gen5

SE

SPS

x128

  • 4x PMSM VdQ / BLDC

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

VC707_2-EX-0001-3_3_4_807-eHSx128_Gen5_PMSM_IOConfig1-55-35

OP5607_300_eHS_Gen5_x128_Machines_SE_withIOs_rtxsg



Virtex-7 VC707 - eHS

1.1.0

Gen4

SE*

SPS

x128

x64

x32

  • 4x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM

  • 2x SRM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 4x Resolver and Encoder

VC707_2-EX-0001-3_3_2_804-eHSx128_Gen4_Motors_with_IOs-53-11

OP5607_300_eHSx128Gen4_withMotorsAndIOs

 

OP4512/OP4610

OP4512/OP4610

Part
Number

Details

Version

Generation
Workflow*

eHS licence
class

Machines

Miscellaneous Features

Quad Encoder Resolver

Bitstream
Source File

 

Kintex-7 410T - eHS 

1.6.0

Gen4

SE

SPS

x128

x64

x32

  • 2x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_4-EX-0001-3_3_4_807-eHSx128_Gen4_Machines_IOConfig2-3C-11

OP4510_400_eHS_Gen4_x128_Machines_SE_IOConfig2_rtxsg

 

Kintex-7 410T - eHS 

1.3.0

Gen4

SE

SPS

x128

x64

x32

  • 2x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM with Saturation

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_4-EX-0001-3_3_4_807-eHSx128_Gen4_Induction_Machines_IOConfig2-22-26

OP4510_400_eHS_Gen4_x128_Induction_Machines_SE_IOConfig2_rtxsg

 

Kintex-7 410T - eHS 

1.5.0

Gen4

SE

SPS

x128

x64

x32

  • 2x PMSM Spatial Harmonics

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_4-EX-0001-3_3_4_807-eHSx128_Gen4_PMSMSH_IOConfig2-3E-11

OP4510_400_eHS_Gen4_x128_PMSMSH_SE_IOConfig2_rtxsg

 

Kintex-7 410T - eHS 

1.2.1

Gen5

SE

SPS

x128

  • None

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • None

TE0741_4-EX-0001-3_3_4_807-eHSx128_Gen5_IOConfig2-FB-12

OP4510_400_eHS_Gen5_x128_Lite_IOConfig2_rtxsg

 

Kintex-7 410T - eHS

N/A

Gen4

SPS

x64

x32

 

  • 2x PMSM Spatial Harmonics

  • 2x Generic Machine SCIM/DFIM

  • 1x SRM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 2x Resolver and Encoder

TE0741_4-EX-0001-3_2_10_45-eHSx64gen4_PMSMSH_with_IOs-41-04

OP4510_400_eHSGen4_Motors_PMSMSH_withIOs_rtxsg

OP4510

OP4510

Part Number

Details

Version

Generation
Workflow*

eHS licence class

Machines

Miscellaneous Features

Quad Encoder Resolver

Bitstream
Source File

FW303-K31

Kintex-7 325T - eHS

1.10.0

Gen4

SE

SPS

x64 x32

  • 2x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_3-EX-0001-3_3_4_807-eHSx64_Gen4_Machines_IOConfig1-3B-45

OP4510_300_eHS_Gen4_x64_Machines_SE_IOConfig1_rtxsg

 

Kintex-7 325T - eHS

1.6.0

Gen4

SE

SPS

x64 x32

  • 2x PMSM VdQ / BLDC

  • 4x Generic Machine SCIM/DFIM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_3-EX-0001-3_3_4_807-eHSx64_Gen4_Machines_IOConfig2-3F-11

OP4510_300_eHS_Gen4_x64_Machines_SE_IOConfig2_rtxsg

FW304-K31

Kintex-7 325T - eHS

1.8.0

Gen4

SE

SPS

x32

  • 2x PMSM Spatial Harmonics

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 1x Resolver and Encoder Reserved per machine

TE0741_3-EX-0001-3_3_4_807-eHSx32_Gen4_PMSMSH_IOConfig1-02-14

OP4510_300_eHS_Gen4_x32_PMSMSH_SE_IOConfig1_rtxsg

 

Kintex-7 325T - eHS

1.1.0

Gen4

SE*

SPS

x64
x32

 

  • 2x PMSM VdQ / BLDC

  • 2x Generic Machine SCIM/DFIM

  • 1x SRM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 2x Resolver and Encoder

TE0741_3-EX-0001-3_3_2_804-eHSx64_Gen4_Motors_with_IOs-43-08

OP4510_300_eHSGen4_Motors_PMSMVDQ_withIOs_rtxsg

 

Kintex-7 325T

1.0.0

Gen4

SE*

SPS

x64
x32

 

  • 2x PMSM Spatial Harmonics

  • 2x Generic Machine
    SCIM/DFIM

FPGA Scope
Thermal Losses
1-D Lookup table
SFP - inter FPGA-link
MUSE

  • 2x Resolver and Encoder

TE0741_3-EX-0001-3_3_2_804-eHSx64_Gen4_PMSMSH_with_IOs-44-08

OP4510_300_eHSGen4_Motors_PMSMSHnoSRM_withIOs_rtxsg

Note: Gen3 is not supported anymore

*Note: Custom firmware descriptions allow external models to be integrated into the Schematic Editor Workflow.

Standard IO config

Hardware

Description

Slot 1A

Slot 1B

Slot 2A

Slot 2B

Slot 3A

Slot 3B

Slot 4A

Slot 4B

IO Extension

Hardware

Description

Slot 1A

Slot 1B

Slot 2A

Slot 2B

Slot 3A

Slot 3B

Slot 4A

Slot 4B

IO Extension

OP5707

OP5650

IOConfig1

16 AO - OP5330-3

16 AI - OP5340

32 DI - OP5353

32 DO - OP5360-2

16 AO - OP5330-3

16 AO - OP5330-3

32 DI - OP5353

32 DO - OP5360-2

n/a

OP5707

OP5650

IOConfig2

16 AO - OP5330-3

16 AI - OP5342

32 DI - OP5353

32 DO - OP5360-2

16 AO - OP5330-3

16 AO - OP5330-3

32 DI - OP5353

32 DO - OP5360-2

n/a

OP4510

OP4512

OP4610

IOConfig1
(legacy)

32 DI - OP5353

32 DO - OP5360-2

16 AI - OP5340

16 AO - OP5330-3

n/a

n/a

n/a

n/a

RS422 6DI 6DO

OP4510

OP4512

OP4610

IOConfig2

32 DIO - OP5369

16 AO - OP5330-3

16 AI - OP5342

16 AO - OP5330-3

n/a

n/a

n/a

n/a

RS422 6DI 6DO

 

(1) Does not support BLDC modelling.

(2) Does not support Synchronous Machine and Double squirrel cage machine modelling.

(3) PWMO frequency on eHS Gen5 firmware is four times its set value.

Compatible IO config

All above mentioned firmwares support the "Polymorphism" feature. The cards listed below are compatible at the same location/slot.



16 Analog Out

16 Analog In

32 Digital In

32 Digital Out

32 Digital In/Out

Io Extension



16 Analog Out

16 Analog In

32 Digital In

32 Digital Out

32 Digital In/Out

Io Extension

Compatible cards

OP5330-3

OP5330-1

 

OP5340-1

OP5340-2

OP5353

OP5351

OP5357

OP5358-3

OP5358-5

OP5360-2

OP5352

OP5354

OP5355

OP5356-3

OP5356-5

OP5359

OP5360-1

OP5360-3

OP5369

RS422 6DI 6DO - OP5969-1

OP5969-2 6TX/6RX Fiber Optic

To activate the Polymorphism, the parameter "Disable strict hardware mismatch validation" must be set to true in the FPGA configuration (OPAL-RT Board or OpCtrl)

 

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter