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OP7000 Troubleshooting
Problem | Possible Causes | Solutions |
---|---|---|
The OP7160 board is not detected when the model is loaded | The OP7000 is not on | Ensure that the switch at the back of the OP7000 is ON |
Verify that the LEDs are ON on the front plates of the boards installed in the front of the chassis. | ||
The simulator was not turned on before the target | Shutdown the target and repeat the “power-up procedure” | |
The PCIe cable is not connected between the simulator and the target | Shutdown the target and the OP7000, connect the PCIe cable, and repeat the “power-up procedure” | |
“Timeout waiting for valid bit” messages appear when executing the model | Models linked to the OP7160 must be in XHP mode | Reset the model, select XHP mode in the Assignation tab and restart the model |
The model was incorrectly stopped during previous use (ex. the OP7000 was shut down with the model still running) | Reboot the target and relaunch the model | |
Loading the model generates error messages concerning polling mode or multiple synchronization sources and inputs/outputs do not work when executed | Models linked to the OP7160 must be in “Hardware Synchronized” simulation mode | Reset the model, select the Hardware Synchronized simulation mode in the Execution tab and restart the model. |
Some inputs/outputs do not work | Incorrect connections at the rear of the OP7000 | Verify that the boards’ LEDs are ON at the front of the OP7000. If needed, use the RJ45 connectors and the monitoring panel to check signals |
Double-check the pin assignment of the rear boards and the connections with the external device. | ||
Signal routing errors in the model | Check the model. Use the integration model delivered with the system as a reference | |
The FPGA configuration file (.conf) is not in the model’s directory | Recopy the file included with the integration model into your folder | |
Damaged board or channel | If the OP7160 was a prototype board, refer to the factory test report for non-working channels | |
Use the integration model to test all channels |
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