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VSC FPGA Port Block

Introduction

This block sends the parameter and CPU signals to FPGA. Also, it receives signals sent by FPGA to CPU. The input and output signals will be packed and unpacked based on the block setting.

 

Mask and Parameters

input dimension

NameDescriptionUnit and rangeParameters compatibility check

Controller Name

Link to OpCtrl and bitstream

N/A

N/A

Number of single SM: nbSM1

Number of single SMs.

  • This number should be the same number that is defined in "VSC FPGA Parameter" block.

no unit

N/A

with (check) without (uncheck) MMC SM

Check if there are cascaded SMs in the model.

Uncheck if there is not any cascaded SMs in the model.

N/A

N/A

Dimension of dc current input: dIdc

Dimension of dc charging current.

  • This dimension should be equal to nbC that is defined in "VSC FPGA Parameter" block.

no unit

N/A

Dimension of DAB sm inputs: dDAB

Dimension of DAB/MAB SMs.

  • This dimension should be equal to dDAB = nbT5*5+ nbT4*4+ nbT3*3+ nbT2*2 which should be in accordance with setting in "VSC FPGA Parameter" block.

no unit

N/A


output dimension

NameDescriptionUnit and rangeParameters compatibility check

nb of sm Vs

Number of SM voltages to be sent to output.

These only include voltages of SMs that are connected to interface nodes, i.e., not  DAB/MAB SMs.

  • This number is equal to nbSM1 + 3*nbSM2.

no unit

N/A

nb of Vcap

Number of capacitor voltages to be sent to output.

  • This number is equal to nbC.

no unit

N/A

nb of DAB for DAB current

Number of MABs which their currents are sent to output.

  • This number is equal to nbT5+nbT4+nbT3+nbT2

N/A

N/A


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Inputs, Outputs and Signals Available for Monitoring

Inputs

NameDescriptionUnit and rangeParameters compatibility check

cfg

Configuration signal from 'VSC FPGA parameter' block

N/A

N/A

SMIs

Ac currents of single SMs with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive nbSM1 signals (currents).

Ampere

  • More elements than nbSM1: if the size of vector sent to this port is greater than nbSM1, extra elements in the end are removed.
  • More elements than nbSM1: if the size of vector sent to this port is less than nbSM1, missing elements are filled with 0's.

SMref

Reference voltages of single SMs with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive nbSM1 signals.

range [-1, 1]

  • More elements than nbSM1: if the size of vector sent to this port is greater than nbSM1, extra elements in the end are removed.
  • More elements than nbSM1: if the size of vector sent to this port is less than nbSM1, missing elements are filled with 0's.

SMen

Enable signals of single SMs with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive nbSM1 signals.

Boolean

  • More elements than nbSM1: if the size of vector sent to this port is greater than nbSM1, extra elements in the end are removed.
  • More elements than nbSM1: if the size of vector sent to this port is less than nbSM1, missing elements are filled with 0's.

Idc

dc charging current flows from external circuit into the capacitor with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive nbC signals.

Ampere

  • More elements than nbC: if the size of vector sent to this port is greater than nbC, extra elements in the end are removed.
  • More elements than nbC: if the size of vector sent to this port is less than nbC, missing elements are filled with 0's.

DABphase

DAB/MAB phase shifts sent to MAB SMs, with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive dDAB = nbT5*5+ nbT4*4+ nbT3*3+ nbT2*2 signals.

range [-0.5, 0.5]

  • More elements than dDAB: if the size of vector sent to this port is greater than dDAB, extra elements in the end are removed.
  • More elements than dDAB: if the size of vector sent to this port is less than dDAB, missing elements are filled with 0's.

DABen

DAB/MAB enable signals sent to MAB SMs, with the same order defined in 'VSC FPGA parameter' block.

  • This port expects to receive dDAB = nbT5*5+ nbT4*4+ nbT3*3+ nbT2*2 signals.

Boolean

  • More elements than dDAB: if the size of vector sent to this port is greater than dDAB, extra elements in the end are removed.
  • More elements than dDAB: if the size of vector sent to this port is less than dDAB, missing elements are filled with 0's.

mmcIs

Ac currents of cascaded SMs with the following order : [ph-a ph-b ph-c]

  • This port expects to receive 3 signals.

Ampere

  • More elements than 3: if the size of vector sent to this port is greater than 3, extra elements in the end are removed.
  • More elements than 3: if the size of vector sent to this port is less than 3, missing elements are filled with 0's.

mmcref

Reference voltages of cascaded SMs with the following order : [ph-a ph-b ph-c]

  • This port expects to receive 3 signals.

range [-1, 1]

  • More elements than 3: if the size of vector sent to this port is greater than 3, extra elements in the end are removed.
  • More elements than 3: if the size of vector sent to this port is less than 3, missing elements are filled with 0's.

mmcen

Enable signals of cascaded SMs with the following order : [ph-a ph-b ph-c]

  • This port expects to receive 3 signals.

Boolean

  • More elements than 3: if the size of vector sent to this port is greater than 3, extra elements in the end are removed.
  • More elements than 3: if the size of vector sent to this port is less than 3, missing elements are filled with 0's.

Outputs

This block has one output port, Out,  with the following variables:

NameDescriptionUnit

Vs

Vectors of SM source voltages Vsp and Vsn for positive and negative current, respectively.

  • The dimensions of Vsp and Vsn are equal to the number defined in "nb of sm Vs" defined in the "output dimension" tab of Block. 
Volt

Vc

Vector including capacitor voltages.

  • The dimension of this vector is equal to the number defined in "nb of Vcap" defined in the "output dimension" tab of Block Mask.
Volt

Idab

Vectors of DAB/MAB currents as :

  • 'winding1': vector of winding 1 currents of DAB/MABs with the same order defined in 'VSC FPGA parameter' block, i.e., [MAB5-winding 1, MAB4-winding 1, MAB3-winding 1, MAB2-winding 1].
  • With the same order and unit  'winding2', 'winding3', 'winding4', 'winding5' are the vector of currents associated with winding 2, winding 3, winding 4, and winding 5 of DAB/MABs, respectively.
  • The dimension of each vector is equal to the number defined in "nb of DAB for DAB current" defined in "output dimension" tab of Block Mask.
p.u.

Description

FPGA bitstream file (*.opbin or .bin) file is defined in "OpCtrl" block which is placed in the same level in the model.


Limitations


References


See Also

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
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