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VSC FPGA Port Block
Introduction
This block sends the parameter and CPU signals to FPGA. Also, it receives signals sent by FPGA to CPU. The input and output signals will be packed and unpacked based on the block setting.
Mask and Parameters
input dimension
Name | Description | Unit and range | Parameters compatibility check |
---|---|---|---|
Controller Name | Link to OpCtrl and bitstream | N/A | N/A |
Number of single SM: nbSM1 | Number of single SMs.
| no unit | N/A |
with (check) without (uncheck) MMC SM | Check if there are cascaded SMs in the model. Uncheck if there is not any cascaded SMs in the model. | N/A | N/A |
Dimension of dc current input: dIdc | Dimension of dc charging current.
| no unit | N/A |
Dimension of DAB sm inputs: dDAB | Dimension of DAB/MAB SMs.
| no unit | N/A |
output dimension
Name | Description | Unit and range | Parameters compatibility check |
---|---|---|---|
nb of sm Vs | Number of SM voltages to be sent to output. These only include voltages of SMs that are connected to interface nodes, i.e., not DAB/MAB SMs.
| no unit | N/A |
nb of Vcap | Number of capacitor voltages to be sent to output.
| no unit | N/A |
nb of DAB for DAB current | Number of MABs which their currents are sent to output.
| N/A | N/A |
Keep one line to create space with the next section
Inputs, Outputs and Signals Available for Monitoring
Inputs
Name | Description | Unit and range | Parameters compatibility check |
---|---|---|---|
cfg | Configuration signal from 'VSC FPGA parameter' block | N/A | N/A |
SMIs | Ac currents of single SMs with the same order defined in 'VSC FPGA parameter' block.
| Ampere |
|
SMref | Reference voltages of single SMs with the same order defined in 'VSC FPGA parameter' block.
| range [-1, 1] |
|
SMen | Enable signals of single SMs with the same order defined in 'VSC FPGA parameter' block.
| Boolean |
|
Idc | dc charging current flows from external circuit into the capacitor with the same order defined in 'VSC FPGA parameter' block.
| Ampere |
|
DABphase | DAB/MAB phase shifts sent to MAB SMs, with the same order defined in 'VSC FPGA parameter' block.
| range [-0.5, 0.5] |
|
DABen | DAB/MAB enable signals sent to MAB SMs, with the same order defined in 'VSC FPGA parameter' block.
| Boolean |
|
mmcIs | Ac currents of cascaded SMs with the following order : [ph-a ph-b ph-c]
| Ampere |
|
mmcref | Reference voltages of cascaded SMs with the following order : [ph-a ph-b ph-c]
| range [-1, 1] |
|
mmcen | Enable signals of cascaded SMs with the following order : [ph-a ph-b ph-c]
| Boolean |
|
Outputs
This block has one output port, Out, with the following variables:
Name | Description | Unit |
---|---|---|
Vs | Vectors of SM source voltages Vsp and Vsn for positive and negative current, respectively.
| Volt |
Vc | Vector including capacitor voltages.
| Volt |
Idab | Vectors of DAB/MAB currents as :
| p.u. |
Description
FPGA bitstream file (*.opbin or .bin) file is defined in "OpCtrl" block which is placed in the same level in the model.
Limitations
References
See Also
OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
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