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VSC FPGA Parameter Block

Owned by Sylvain Ménard
Last updated: Jan 23, 2024 by Juan Paez-Alvarez
10 min read

Introduction

This block defines the parameter of voltage source converter modeled in FPGA. This block is put in console submodule, and the parameter value can be modified during real-time simulation.  This block can model different converter topologies, including cascaded half-/ full-bridge submodule and dual-/multi-active bridge converters. The submodule and capacitor index can be easily configured to accommodate different converter combinations, e.g., ac-dc, dc-ac, ac-dc-ac or solid-state transformer.

The ac/ac circuit shown in Figure 1 is an example for the implementation of the VSC FPGA model. The circuit has three stages of power conversion, i.e., ac/dc stage, dc/dc stage, and dc/ac stage. A single-phase converter unit with only switching parts and excluding capacitor is called sub-module (SM). In the current version, the block only supports half-bridge (HB) and full-bridge (FB), as shown in Figure 2. In this block SMs are divided into three categories, i.e., DAB/MAB SMs, single SMs, and cascaded SMs. DAB/MAB SMs are SMs that connected to DAB/MAB transformer on their ac side, e.g., SM16 to SM36 in Figure 1. It is worth mentioning that DAB/MAB SMs are considered as a part of DAB/MABs. Single SMs are SMs that their ac side is connected to one interface node (not DAB/MAB), e.g., SM1 to SM3 in Figure 1. Cascaded SMs are SMs that their ac side are connected in series to one ac interface node (not DAB/MAB), e.g., SM4 to SM15 in Figure 1.

Unlike VSC CPU block in which a capacitor can be simulated either internally or externally, in VSC FPGA block all capacitors are considered as internal capacitors. The OPAL VSC FPGA model may also include the multiple multi active bridge (MAB) and dual active bridges (DAB), e.g. the middle stage of dc/dc converter in Figure 1.


Figure. 1 Example of VSC FPGA with ac-dc, dc-dc and dc/ac conversion stages 

 Figure. 2 Types of supported sub-modules in the current version

Mask and Parameters

Cap


NameDescriptionUnit and rangeParameter Compatibility Check

number of cap, nbC

A number defines number of capacitors (nbC) in the model.

  • Current version supports maximum of 128 capacitors.
  • Unlike VSC CPU model, all capacitors are simulated internally.
  • no unit

N/A

Cap (pu) (an array of 1*nbC)

A row vector including capacitor values in p.u.

The dimension of this vector is nbC. The value of i-th element being Ci means the capacitance of i-th capacitor is Ci p.u.

  • p.u (normalized)
  •  and positive

N/A

Discharge resistance in parallel with cap (pu) (an array of 1*nbC)

A row vector including resistance of capacitor discharge resistor values in p.u.

The dimension of this vector is nbC. The value of i-th element being Ri means the discharge resistor of i-th capacitor has the value of Ri p.u.

  • p.u (normalized)
  •  and positive

N/A

Capacitor base voltage (V) (an array of 1*nbC)

A row vector including capacitors base voltages.

The dimension of this vector is nbC. The value of i-th element being Vbi means i-th capacitor has the base voltage of Vbi Volt.

  • Volt
  • positive

N/A

SM power base (VA) (an element with same value for all SM)

Defines base power for all SMs.

The dimension is 1 and all SMs will have the same base power.

  • VA

N/A

Vcap mode

Sets capacitor operation mode

Four available options are:

  • Vcap reset = 0
  • Normal operation
  • Reserved
  • Vcap set to a fixed value

N/A

N/A

Vcap fixed value (pu)

defines fixed capacitor voltage in p.u. which will be effective when "Vcap set to a fixed value" is selected.

  • This option emulates an ideal voltage control.
  • p.u.
  • non-negative number in the range of 0 to 4

N/A

SM

NameDescriptionUnit and rangeParameter Compatibility Check

Number of non-MMC  SM: nbSM1

Number of single SMs

  • Current version supports maximum of 64 single SMs.
  • no unit

N/A

Number of MMC SM per valve: nbSM2

Number of cascaded SMs per valve.

  • In Current number of valves =3.

Total number of single and cascaded SMs should be less than 128, i.e., nbSM = nbSM1 + 3*nbSM2<=128.

  • no unit

N/A

SM type

A row vector including defines single and cascaded SMs type.

Elements of this array are either 0 or 1, where 0 represents HB SM and 1 represents FB SM.

The dimension of this vector is nbSM (i.e., nbSM1 + 3*nbSM2), where where i-th element being 0 or 1 means i th SM is HB or FB, respectively.

no unit

N/A

Cap index of SM

A row vector defines connection between the SM and the capacitor. The position of an index in the vector identifies the selected SM, and the index value identifies the designated capacitor.

The dimension of this vector is nbSM (i.e., nbSM1 + 3*nbSM2), where where i-th element being k means i th SM is connected to k-th capacitor.

  • no unit. 
  • integers between 1 and nbC.

N/A

DAB


NameDescriptionUnit and rangeParameter Compatibility Check

Number of DAB with 5-winding transformers, nbT5

Number of 5-SM MAB (also called MAB5). They include 5 active bridges each connected to a winding of 5-winding transformer.

  • Current version supports maximum of 64 MAB5 modules, nbT5<=64.
  • if there is no MAB5 in the model, nbT5=0.
  • no unit
  • non-negative integer <=64

N/A

Cap index of 5-winding DAB SM

A matrix which defines connection between the SMs of MAB5s and the capacitors. 

The dimension of this matrix is nbT5 *5, where the value of entry (i , j) being k (an integer between 1 and nbC) means k-th capacitor is connected to j-th winding of i-th MAB5.

  • no unit. 
  • integer between 1 and nbC.

N/A

Number of DAB with 4-winding transformers, nbT4

Number of 4-SM MAB (also called MAB4). They include 4 active bridges each connected to a winding of 4-winding transformer.

  • Current version supports maximum of 64 MAB4 modules, nbT4<=64.
  • if there is no MAB4 in the model, nbT4=0.
  • no unit
  • non-negative integer <=64

N/A

Cap index of 4-winding DAB SM

A matrix which defines connection between the SMs of MAB4s and the capacitors. 

The dimension of this matrix is nbT4 *4, where the value of entry (i , j) being k (an integer between 1 and nbC) means k-th capacitor is connected to j-th winding of i-th MAB4.

  • no unit. 
  • integers between 1 and nbC.

N/A

Number of DAB with 3-winding transformers, nbT3

Number of 3-SM MAB (also called MAB3). They include 3 active bridges each connected to a winding of 3-winding transformer.

  • Current version supports maximum of 64 MAB3 modules, nbT3<=64.
  • if there is no MAB3 in the model, nbT3=0.
  • no unit
  • non-negative integer <=64

N/A

Cap index of 3-winding DAB SM

A matrix which defines connection between the SMs of MAB3s and the capacitors. 

The dimension of this matrix is nbT3 *3, where the value of entry (i , j) being k (an integer between 1 and nbC) means k-th capacitor is connected to j-th winding of i-th MAB3.

  • no unit. 
  • integers between 1 and nbC.

N/A

Number of DAB with 2-winding transformers, nbT2

Number of 2-SM MAB (also called DAB). They include 2 active bridges each connected to a winding of 2-winding transformer.

  • Current version supports maximum of 64 DAB modules, nbT2<=64.
  • if there is no DAB in the model, nbT2=0.

Note: In the current version, total number of MABs should be <=64, i.e.,  nbT5+nbT4+nbT3+nbT2<=64

  • no unit
  • non-negative integer <=64

N/A

Cap index of 2-winding DAB SM

A matrix defines connection between the SMs of DABs and the capacitors. 

The dimension of this matrix is nbT2 *2, where the value of entry (i , j) being k (an integer between 1 and nbC) means k-th capacitor is connected to j-th winding of i-th DAB.

  • no unit. 
  • integers between 1 and nbC.


Transformer winding leakage inductance

A matrix which defines inductance connected to each branch of MAB transformer (including leakage inductance).

The dimension of this matrix is dDAB *2, i.e., dDAB = 5*nbT5+4*nbT4+3*nbT3+2*nbT2, where each row is assigned to one MAB ( i-th row corresponds to i-th MAB), while column 1 is reserved for inductance of winding 1, and column 2 is reserved for inductance of windings 2, 3, 4, 5.

  • In the current version, it is assumed that inductances of windings 2, 3, 4, 5 are equal.
  • p.u. 

N/A

Transformer winding resistance inductance

A matrix which defines resistance connected to each branch of MAB transformer.

The dimension of this matrix is dDAB *2, i.e., i.e., dDAB = 5*nbT5+4*nbT4+3*nbT3+2*nbT2, where each row is assigned to one MAB ( i-th row corresponds to i-th MAB), while column 1 is reserved for resistance of winding 1, and column 2 is reserved for resistance of windings 2, 3, 4, 5.

  • In the current version, it is assumed that resistances of windings 2, 3, 4, 5 are equal.
  • pu


Reset DAB current to 0

if checked, DAB/MAB currents are forced to 0.

N/A

N/A


control

NameDescriptionUnit and rangeParameter Compatibility Check

frequency of carrier 1, 2, 3

Defines carrier frequency of DAB/MAB and single SMs SMs (excluding cascaded SMs) belong to group 1, 2, 3.

  • Each group has different carrier frequency than other groups.

Hz

N/A

Number of DAB [0, 128]

Number of DAB/MAB included in group 1, 2, 3.


  • no unit.
  • non-negative integer <=64

N/A

Number of ac/dc SM [0, 128]

Number of single SMs included in group 1, 2, 3.


  • no unit.
  • non-negative integer <=128

N/A

frequency of carrier 4

Defines carrier frequency of cascaded SMs and reminder of single SMs and DAB/MAB.


Hz

N/A

advanced

NameDescriptionUnitParameter Compatibility Check

Permanent fault


If checked, when capacitor of SM is shorted during the operation, fault will be triggered and latched.

Unchecking this option will allow capacitor voltage to be recharged after fault is cleared.

N/A

N/A

FPGA clock


FPGA clock period

s

N/A

Vs average value over TsCPU/ instantaneous value


If checked, Vs sent from FPGA to CPU (at each CPU time step) is averaged over one CPU time step.

If it is unchecked, the instantaneous value of Vs is sent at each CPU time step.

N/A

N/A

Inputs, Outputs and Signals Available for Monitoring

Inputs

There is no input for this block.

Outputs

NameDescription

SST_fpga_conf

Valve configuration signal that send to VSC_fpga_port block.

Description

VSC topology is made of same basic components, which are defined below so the user can flexibly configure them to form different VSC topologies.

SM:

The term sub-module (SM) is borrowed from the modular multi-level converter (MMC) referring to the basic unit consisting of several switches (IGBT/diode) and capacitors. Typical SM include Half-bridge (HB) SM, full-bridge (FB) SM, clamp-double (CD) SM, T-type SM (T-SM), and etc. In this block, SM is defined slightly different than the SM in an MMC. SM in this block only includes the switches part of a converter unit and doesn't include the capacitor. Normally, in VSC, the dc side of SM is connected to a capacitor and the ac side of SM is connected to either a DAB/MAB transformer or an interface node.

Capacitor:

Unlike VSC CPU block in which a capacitor can be simulated either internally or externally, in VSC FPGA block all capacitors are considered as internal capacitors. 

DAB/MAB:

The converter can include MAB converters, in specific case of having two active bridges it is called dual active bridge (DAB). A DAB/MAB consists of several SMs, inductor/resistor and transformer. In this block, SM connected to DAB/MAB is called DAB/MAB SM.

Interface node:

an interface node is a node connecting the ac side of SM and the external circuit.

How to configure the converter topology in this model?

  1. Properly configure the converter by setting the right parameters of this block. This block computes all internal voltages and currents and also updates state variables.
  2. Identify the number of SM, single SM, cascaded SM per valve, DAB/MAB SM, capacitors, number of DAB/MAB, and number of interface node, number of 5-SM MAB, also called MAB5, number of 4-SM MAB, also called MAB4, 3-SM MAB, also called MAB3, and 2-SM MAB, also called DAB.
    1. nbSM: number of SM
    2. nbSM1: number of single SM
    3. nbSM2: number of cascaded SMs per valve
    4. dDAB: total number of DAB/MAB SM
    5. nbC: number of capacitor
    6. nbMAB: number of DAB/MAB
    7. nbNode: number of interface node
    8. nbT5: number of 5-SM MAB
    9. nbT4: number of 4-SM MAB
    10. nbT3: number of 3-SM MAB
    11. nbT2: number of 2-SM MAB, i.e., DAB
  3. Name each SM, capacitors, DAB/MAB, and nodes in numerical order:
    1. SM-1, SM-2, … SM-nbSM;
    2. C-1, C-2, ..., C-nbC;
    3. Node-1, Node-2, ..., Node-nbNode;
    4. For MAB numbering, numbering starts from 1 up nbMAB= nbT5+nbT4+nbT3+nbT2. Numbering of MABs is started from MAB5 modules, followed by MAB4 and MAB3 modules and ends with MAB2 modules, where MAB5 modules are the lowest numbered MABs and MAB2 modules are the highest numbered MABs, as: MAB5-1, MAB5-2, ..., MAB5-nbT5, MAB4-1, MAB4-2, ..., MAB4-nbT4, MAB3-1, MAB3-2, ..., MAB3-nbT3, MAB2-1, MAB2-2, ..., MAB4-nbT2. 
  4. Define number and values of capacitors in 'Cap' tab.
  5. Connect single and cascaded SMs with capacitor in 'SM' tab. Also, the type of SM, HB or FB, should be defined in this tab
    1. In 'Cap index of SM': define a row vector with the dimension of nbSM1+3*nbSM2, where i-th element represents value of capacitor (in p.u.) connected to SM-i.
    2. In 'SM type': define a row vector with the dimension of nbSM1+3*nbSM2, where i-th element is 0 or 1 if SM-i is HB SM or FB SM, respectively. 
  6. Connect DAB/MAB with capacitor in 'DAB' tab.
    1. In Cap index of 5-winding transformer define a matrix with the dimension of nbT5*5, where the value of entry (i , j) represents the value of capacitor (in p.u.) connected to j-th winding of i-th MAB5. The similar procedure should follow to connect DAB/MAB to capacitor, i.e., for 4-winding the matrix has the dimension of nbT4*4, for 3-winding the matrix has the dimension of nbT3*3, and for 2-winding the matrix has the dimension of nbT2*2.
  7. Set other parameters properly in the mask.

Limitations

The current version, has following limitations:

  • maximum of 128 capacitors are supported.
  • Total number of single and cascaded SMs should be less than 128.
  • Total number of single and cascaded SMs should be less than 64.
  • Up to 5-SM MAB is supported. 
  • The DAB/MAB transformer model used in this block is an ideal transformer with leakage inductance and resistance. The transformer magnetizing branch is not considered. 

References

[1] W. Li and J. Bélanager, "An Equivalent Circuit Method for Modelling and Simulation of Modular Multilevel Converters in Real-Time HIL Test Bench", IEEE trans. Power Delivery, vol. 31, no. 5, pp. 2401-2409, Oct. 2016.

See Also

VSC Configuration Block, VSC FPGA Port Block.

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