This test is designed to determine whether the Vcap modes can work properly or not. There are 3 working modes of V_cap (More details about V_cap mode are related in section 2.1.3); the modes are tested in the following sections.

Vcap Mode 0 Test and Further Test of Gate Signals Block

Vcap mode 0 test is to test whether the cells can be charged or discharged correctly when the capacitors are normally operated. In order to achieve the test purpose, we can observe the values variation of the Vmmc when the cells are charged and discharged by a certain arm current pulse.

• Test of cells charging
1. System initialization.
2. Set the number of cells per arm wanted to be tested in MMC Parameter block, and change the capacitor voltage base Vb accordingly. For example, here the number of cells per arm is set to 10, Vb is set to 10.
3. Change the V_cap mode to 0: normal operation.
4. To generate an arm current pulse with magnitude 0.1 and duration of 0.01s, set up the Arm Current Generation block as its initialization.
5. Give ON signals to the first 10 gate switches of 1^st group in the MMC pulse block. In this case, the cells can be charged and discharged by the arm current pulse. Turn on the switch of Arm Current Generation block to charge the cells. If the V_cap value of each cell can be increased by 0.1 (at the same time the V_mmc value increased by 1) every time after turning on the charging switch, it shows that the cells can be charged properly at Vcap model 0.
• Test of cells discharging

For this test, do the same operations as test of cells charging, the only difference is that the arm current pulse will be with magnitude -0.1 and duration of 0.01s in FPGA. We can set up the Arm Current Generation block as Table 4.

Table 4: Arm Current Pulse Generation block setup

Turn on the switch of Arm Current Generation block to discharge the cell. If the V_cap value of each cell can be decreased by 0.1 (at the same time the V_mmc value decreased by 1) every time after turning on the charging switch, it shows that the cells can be discharged correctly at Vcap model 0. It should be noticed that the V_cap will not be negative because of existence of the antiparallel diodes.

• Further test of MMC pulse block
  The further test of MMC pulse block is to determine whether every gate signal vector of MMC pulse block can work correctly or not. This test can be done based on Vcap mode 0.
1. System initialization.
2. Set the number of cells per arm wanted to be tested in MMC Parameter block, and change the capacitor voltage base Vb accordingly. For example, here the number of cells per arm is set to 10, Vb is set to 10. Change the capacitor shunt resistance in MMC Parameter block, for easy testing, set the value of capacitor shunt resistance to 1.
3. Change the V_cap mode to 0: normal operation.
4. To generate a continuous DC arm current with magnitude 0.1, set up the Arm Current Generation block as Table 5.

Table 5: DC Arm Current Generation block setup

           5. Give ON signals to the 1^st 10 gate switches of 1^st group one by one in the MMC pulse block. Every time one gate signal is ON, the corresponding cell is charged. The final V_cap value of the cell is 0.1.

           6. Give OFF signals to the 1^st 10 gate switches of 1^st group one by one in the MMC pulse block. Every time one gate signal is OFF, the corresponding cell is discharged. The final V_cap value of the cell is almost 0 (It should be noted that because the real-time simulation is based on a discrete system, sometimes there is a small calculation error).

Vcap Mode 1 Test

V_cap mode 1 test is to test whether the cells can be set to 0 correctly. To achieve the test purpose, we can observe the value variation of the V_caps, V_mmc and Total V_cap, when there is an arm current charging the cells need to be test.

1. System initialization.
2. Set the number of cells per arm wanted to be tested in MMC Parameter block and change Vb Correspondingly. Change the V_cap mode to 1: V_cap reset to 0.
3. To generate a DC arm current with magnitude 0.1, we can set up the Arm Current Generation block as Table 5.
4. Give ON signals to the first 10 gate switches of 1^st group in the MMC pulse block. The test result is shown as Figure 20f.

It should be noted that because the real-time simulation is based on a discrete system, sometimes there is a small calculation error.

Vcap Mode 3 Test

Output Voltages Are Constant

Vcap mode 3 test is to test whether the cells can be set to the fixed value correctly. To achieve the test purpose, we can do the same thing like section 3.3.2, with changing the Vcap mode to 3.

1. System initialization.
2. Set the number of cells per arm wanted to be tested in MMC Parameter block, and change Vb Correspondingly. Change the V_cap mode to 3: V_cap reset to fixed value, at the same time change the V_cap fix value to 1 (if the V_cap fix value is not changed, this test is totally same as test in section 3.3.2).
3. To generate a DC arm current magnitude 0.1, setup the Arm Current Generation block as Table 3.
4. Give ON signals to the first 10 gate switches of 1^st group in the MMC pulse block. The test result is shown as Figure 21.

Output Voltages Are Sinusoidal Waveforms

We can also check the results with a sinusoidal waveform.

1. System initialization as Table 6:

Table 6: MMC parameter block initialization setup

       2. Set the number of cells per arm wanted to be tested in MMC Parameter block, and change Vb Correspondingly. Change the V_cap mode to 3: V_cap reset to fixed value, at the same time change the V_cap fix value to 1. Enable the pulse.

       3. The test results of Vmmc can be shown below as Figure 22.