HYPERSIM

Software Toolboxes Installed with HYPERSIM

New features

• A newControl Microgrid library is available, offering multiple control blocks:

  • Active Power Dispatch

  • BESS Management

  • Curtailment Management

  • Islanding Management

  • Load Management

  • Reactive Power Dispatch

• External controllers can now be added to HYPERSIM based on the recommendations of the CIGRE B4.82 working group which allows to standardize the integration of real manufacturer code in simulation software.

  • See CIGRE Interface for more details on how to add and configure a CIGRE block to a circuit.

  • See The CIGRE Interface for more details on how to create a CIGRE library.

  • A new example model has been added to demonstrate the CIGRE block using a Forward Euler integrator: Examples | CIGRE integrator .

• A new option has been added that allows to define a number of steps to be executed without IOs at the beginning of the simulation to improve simulation performance.

  • See the “Number of steps before enabling I/Os” option in the https://opal-rt.atlassian.net/wiki/spaces/DOCHS/pages/20189498/Simulation+Settings#Advanced .

  • Note that before that, HYPERSIM was always executing 100 steps without IOs. This new option simply allows to change this value.

• It is now possible to get the license number and target number in the license panel of the Target Manager.

• Python API:

  • A new methodgetVersion is available to get the current HYPERSIM version

  • Multiple new simulation and task mapping settings can now be updated using the setPreference and getPreference methods. These settings are now listed in theSimulation Settings and the Task Manager | Summary and Preferences documentation.

Improvements

• Prevent the creation of an I/O Interface with a duplicated name.

• It is now possible to start/stop the recording of signals directly in the /wiki/spaces/DOCHS/pages/20176638.

  • Note that the control center has to be launched before the simulation has started.

• Error highlight in HYPERSIM console has been improved.

• An error message is now displayed when the network adapter of the localhost target is set to an invalid IP address in the Target Manager.

  • Note that before that, the HYPERSIM engine would simply crash.

• The Target Managerlicense panel now warns when no license is installed.

• The Load Flow Viewer now has a “clear all” contextual menu to clear the content of the “Output” tab.

• Firmware and Hardware mismatches are now clearly stated in the simout console.

Bug fixes

• Fixed an issue where the RT Monitor table was displaying incorrect status in the “Enabled” column when scrolling the table

• Fixed the Start/stop timeout defined in HYPERSIM (Simulation Settings → Advanced → Simulation Server) that was not always correctly taken into account.

• Fixed an issue during analyse when a UCM with selected sensors was duplicated.

• Fixed an issue where the Activation Tool was not responding when applying a license from Help&Support.

• Fixed an issue where the HYPERSIM engine was crashing when analyzing the network from the Load Flow Viewer.

• Fixed an issue where the HYPERSIM engine would crash with certain parameter configuration of the 3-winding, w/sat + tap +dec block. The engine would crash when

  • the Vmin parameter was greater than the Vmax parameter, or

  • the Vnom parameter was not between Vmax and Vmin

• Fixed a HYPERSIM engine crash when a file that is not a .pun was used in line components.

• Fixed an issue that was slowing down the load flow computation in some cases.

• Fixed a bug where load flow properties weren't being saved when the model was saved.

• Fixed an issue where the Frequency Protection block was not taking into account the initial value.

Removed

• Unused G_Ref and P_Ref sensors on Network FACTS and HVDC LCC pulse components were removed.

Signal Visualization and Processing

Dashboards

FPGAScope

• Signal display order in the FPGA Scope now follows the order defined in the FSD file.

• Fixed potential ScopeView crash when making an FPGA Scope acquisition with multiple FPGAs

Unified Database

PowerFactory Import

• Added support of subsystems

  • Documented in https://opal-rt.atlassian.net/wiki/spaces/DOCHS/pages/875528410/PowerFactory+Supported+Features+and+Limitations#Import-of-subsystems

• Added support of the WEHGOV turbine governor blocks

• Added support of the GAST turbine governor blocks

PSS/E Import

• The following components are now imported as native HYPERSIM components

  • IEESGO

  • GGOV1

  • DEGOV

  • IEEEG1

  • ESAC6A

• Added warning message when a model is imported without a dyr file

• Improved import time performance for large models

• Fixed an error in connecting the ESST1A

PSCAD Import

• Fixed an issue when several master:import shared the same name in a given subsystem

• Fixed missing items in the PSCAD input model intermediate library

I/O Interfaces

• Allow signals to be renamed in the I/O Interface Configuration window

• Improved stability by ensuring that asynchronous computation components of I/O interfaces run either on core 0 or on a dedicated core, but not on the core of the simulation itself

CAN

• Added support for the CAN driver using the Kvaser PCIe card

FPGAScope

• Fixed capability to differentiate boards of the same family type

• Fixed crash of simulation when using an RT core

IEC 61850

• Added support for sending a report to multiple MMS client instances

MODBUS Slave

• Added support for TCP slave IDs up to 255

OPAL-RT Board

• Added capability to program multiple OP4810-IO/OP4815-IO platforms in parallel during the load of a model

• Added the display of extra information such as the IP and MAC addresses to the detection of OP4810-IO/OP4815-IO platforms

• Improved workflow by keeping connections even if a raw data point's name changes

• Improved workflow by skipping bitstream programming if OP4810-IO/OP4815-IO platforms are configured with an empty chassis name and/or an empty IP address

• Fixed reload of bitstreams on SGI systems

• Fixed bitstream configuration update mechanism to:

  • keep the name of raw data signals

  • keep the byte and bit offsets of raw data signals

  • keep the state of the ‘Enable FPGA scope’ check-box

  • support merging configurations for OP48H20 cards

• Fixed filter for bitstream file browser

• Fixed wrongly displayed message about firmware mismatch

• Fixed wrongly found hardware mismatch for extra slot of OP4810-IO/OP4815-IO platforms

• Fixed validation of threshold limits for digital channels

Synchronization

• Fixed logs that were referencing the wrong network interface used by the Oregano card

FPGA-Based Power Electronics Toolbox

eHS Blockset