This workflow supports the OP4510 and OP5607

Creating a new RT-LAB Model

Open RT-LAB and follow these steps to create a new RT-LAB project:

1. In the main RT-LAB User Interface, navigate to File > New > RT-LAB Project to open a new project wizard.
2. Enter a project name (e.g. eHS_examples), then click Next.
3. Browse the template directory to select the model to add it to the project. Open the eFPGASIM folder and select Schematic_Editor_Workflow > eHS Gen4> Boost_And_Two_Level_Inverter > OP5607 > Boost_And_Two_Level_Inverter_OP5607.
4. Click Finish to create the new RT-LAB project in the project explorer.
5. The eHS_examples project will be created, and the corresponding RT-LAB model will be imported into the project workspace (in this example, the model is named Boost_And_Two_Level_Inverter.

Editing the model

Before building the model, verify that you can access and edit the model.

Click on Edit the model in the Preparing and Compiling pane.

Model description

The model is composed of two main subsystems:

1. SC_eHS: Subsystem executed by the host computer during the simulation to monitor and control the simulation.
2. SM_eHS: Subsystem executed by the target simulator, in real-time, on the system CPU that communicates with the FPGA board and the physical system I/Os.

SC_eHS

Double click on the SC_eHS block to open the SC_eHS details window.

SM_eHS

Click on the SM_eHS subsystem block to open the SM_eHS details window. This window provides a detailed diagram of the master subsystem.

EHS Block

The eHS block provides an interface to creating new or accessing old FPGA-Based circuits using the OPAL-RT Schematic Editor. Double click on the eHS1 block to open the subsystem mask. Click on Edit to open the Boost2lvl FPGA-Based circuit using the OPAL-RT Schematic Editor.

Building the model

   1. Assign the model on a target simulator by clicking on right clicking on the model. Choose a development node (target simulator) to build the model. The intended target to run this example must be either an OP5607 or OP5707.

   2. In the Preparing and Compiling window, click Build the model. The Building Model window appears.

   3. Verify that the model was successfully built by clicking Consult result in Compilation View.

I/O Interface

Expand the section I/O interfaces and double-click on OPAL-RT Board. Ensure that the Chassis type is selected to either OP5607 (Virtex-7) or OP5707 (Virtex-7) and the Chassis ID matches the ID of the FPGA in your development board.

Loading the model

In the Overview tab, click on Load the model. The console will open, and the real-time code will be uploaded to the simulator. The Loading model window appears briefly during the loading process.

Executing the simulation

Click on Execute the model to start the simulation.

Monitoring the simulation

As soon as you load and execute the model, the Simulink console opens, and you should be able to see the simulation running in the console window.

Ensure that you have a loopback connection between the Digital In and Digital Out cards as shown below.

Double click on the eHS_Outputs_Avg scope to view the outputs of the Two-level and Boost voltages and current.

Stopping the simulation

Click on Reset the model to stop the simulation.