eFPGASIM with RT-XSG Module - Rules and recommendations

If you’re experiencing issues with generated ioconf such as missing blocks, missing connections between blocks or missing ports, consider these few rules and tips.

1. RT-XSG Modules need to have a direct connection between one and another for the automatic generation process to resolve the connection. It is recommend to have NO BLOCKS between to RT-XSG Module features. Try to remove all signal altering blocks between two RT-XSG Module compatible features. A list of blocks are defined as passthrough in RT-XSG and will not interfere with connection processing. These blocks are: (bussing or un-bussing with these blocks might still cause issues):

   1. Register Block

   2. Delay Block

   3. Assert Block

   4. Down Sampler Block

   5. Up Sampler Block

2. Make sure the firmware from which you’re making modifications is based on the firmwares from eFPGASIM 2.15 since modifications were made to the firmware models between eFPGASIM 2.14 and eFPGASIM 2.15 to make all example firmware models compatible with the new RT-XSG Modules compatible blocks.

3. When creating RT-XSG Module feature to be used a libraries, refer to the official RT-XSG Module documentation.

4. When using eFPGASIM custom model toolbox block, refer to the official eFPGASIM FPGA-based custom model documentation.