Selects the type of implementation (inside CPU or FPGA). NB: This parameter must match the value set in the Model Type parameter on the corresponding MMC Valves block. 

Selects the type of model to be used in the CPU: Average Model (AVM)  or Switched Function Model (SFM). NB: This parameter must match the value set on the corresponding MMC Valves block. 

This parameter is only available if the CPU model type is selected as "SFM".  It Specifies the number of capacitors for each valve.

In case of Half-Bridge and Full-Bridge sub-modules, this number is equal to the number of sub-modules per valve. For sub-modules with two capacitors (CD-SM for example) this parameter should be twice the number of sub-modules.  NB: The value of this parameter must match the value set on the corresponding MMC Valves block.

>0 and <1/(4Ts)

Shows the name used in the selected OpCntrl or OpLnk block. The parameter cannot be set manually, it is updated automatically when selecting a OpCntrl / OpLnk block from the list on the OpCntrl / OpLnk block parameter.

Number of gating signals being sent to FPGA from CPU. This parameter is used when the gating signals for the SMs inside the FPGA are generated directly on the CPU instead of using the low level control inside the FPGA or an external controller. This can be useful for debugging purposes.

Since sending gating signals to FPGA takes CPU time, this parameter should have a minimum value to avoid sending unused gating signals.

Specifies in which logical group inside the FPGA the valves are simulated.

It is a bus signal that contains the parameters set coming from the MMC Valves Parameters Block block.

It is a vector containing the high level control signals for the valves, i.e. the modulation index for each valve. The number of elements in the Vref input must be the same as selected in the Number of Valves parameter. The position in the vector indicates the valve being controlled, for example the first element in the vector refers to the modulation index of the first valve, while the 4th element refers to the modulation index of the 4th valve.

According to the type of SMs in the valve the modulation index can be in the range of [ 0 , 1 ] if the valve only contains unipolar SMs (Half Bridge for example) or in the range of [ -1 , 1 ] if the valve has bipolar SMs (Full-bridge for example). Going beyond these ranges could result in unexpected behavior.

It is a bus signal that contains the valves capacitor voltages when the valves are simulated in the CPU-based switched function model. For average model or FPGA-based switched function model the signal is empty.

This port can be connected directly with the Vcap output on the corresponding MMC Valves block. To see the signals inside the bus, please refer to the MMC Valves block documentation. 

CPU implementation

Average Model

For an Average model in CPU, VlvCtrl is a bus signal containing the following signals:

• v1, v2, v3, .... → each of this signals is a bus containing the modulation index for each valve. The signal v1 contains the modulation index for valve 1, the signal v2 the modulation index for valve 2 and so on.  The block takes the data from the Vref  input and organizes it in this bus format. Thus, the VlvCtrl output contains exactly the same contents as Vref but reorganized in a bus form.

Switched function model

For a switched function model implemented in the CPU, VlvCtrl is a bus signal containing the following signals:

• v1, v2, v3, .... → each of this signals is a bus containing the control signals for all the SMs in each valve. The signal v1 contains the controls signals for valve 1, the signal v2 the control signals for valve 2 and so on.  The VlvCtrl input contains as much signals as the number of valves selected in the Number of Valves parameter. For example, if the number of valves is three only v1, v2 and v3 are created but if is 12 then the block creates 12 signals : v1, v2, v3 .... v12. To work properly the number of elements in the input Vref must match the Number of Valves parameter.

Each of the signals v1, v2, v3, ...  is also a bus containing the following signals:

• g1, g2, g3, g4, g5 → each signal is a vector containing the gate signals for each SM switch. The number of elements in the g1 to g5 vectors is equal to the Number of SMs per valve parameter. The elements in each vector (g1 to g5), are organized based on the corresponding SM in each valve. For example, the first element on g1 refers to the control signal of the switch g1 of the first SM, while the 13th element on g4 refers to the control signal of the switch g4 on the 13th SM. For each signal, 1 means the corresponding switch is closed while 0 means that it is open. The SMs are counted from the positive terminal of the valve to the negative terminal, i.e. the first SM being the closest to the positive terminal.  Note that each valve control signal (v1, v2, v3, ... ) has always the five signals g1 to g5, even if the SM does not have all the switches (for example a Half-Bridge SM only has g1 and g2). Thus  for sub-modules with less than 5 switches, a zero is sent to the unneeded gating signals.

FPGA implementation

In the case of a model implementation in the FPGA, the VlvCtrl is an empty signal since the control signals are sent to the model inside the FPGA.

It is a vector signal that contains the average value of the SM capacitors on each valve, i.e. ΣVcap / Nsm. In the CPU model implementations, the block calculates this output taking into account the data in the Vlvmeas and Vcap inputs. In an FPGA implementation, the blocks extracts this data directly from the information sent from the FPGA.

The number of elements in Vcap_ave depends on the number of valves. The position in the vector represents the corresponding valve, i.e. the first element corresponds to the valve number 1, the second to the valve 2 and so on.

This output is given in per unit. For FPGA implementations the capacitor voltages are saturated at 4 p.u.

This signal contains the individual data of some of the SMs inside the FPGA to be scoped.  Thus, in the CPU implementations this signal is empty.

The sctructure of the Scope output is two buses:

• vlv1to6 → it is a bus signal that contains the data of SMs in valves 1 to 6.
• vlv7to12 →  it is a bus signal that contains the data of SMs in valves 7 to 12. It is available only if Number of Valves is greater than 6. The signal format is the same as vlv1to6.

Note that the Scope output always gives information by groups of 6 valves (vlv1to6 and optionally vlv7to12), independently of the number of valves. For example if Number of Valves = 3, the Scope signal will provide data as if there was 6 valves. In that case only the data of valves 1 to 3 is meaningful.