Description

This block simulates a set of MMC valves. The block can simulate up to 12 valves. Three different models are supported: CPU-based Average Model, CPU-based switched function model and FPGA-based switched function model.

In the average model, for each valve, the sub-module (SM) capacitors are replaced by one equivalent capacitor representing the total energy stored in the valve. In the switched function model, the individual SM control and voltages are modeled.

In the MMC valves, the switched function model can be implemented inside the simulator CPU or inside the FPGA. When using CPU implementation the time step is limited to some tens of microseconds (depending of the complexity of the system and number of SMs to be simulated). In the FPGA implementation, the simulation time step for the SMs can be decreased below 1 microsecond.

Figure 1. MMC Valves block overview.

The total number of SMs per valve is limited in CPU implementation by the simulation time step. For FPGA implementation it depends on the user license but up to 511 SMs are supported per valve in current version of the firmware. More SMs can be supported under request.

This block must be used together with the MMC Valves Parameters Block and MMC Valves Low Level Control Block blocks. The first one sets some of the parameters to the MMCValves block while the second allows the user to create the appropriate inputs for the block.

Mask and Parameters

Figure 2. MMC Valves block mask. On the left, the mask shows the parameter related to CPU model implementation. On the right, the mask shows the parameters related to the FPGA implementation.

General Parameters

The following table presents the block parameters that are common for both CPU as well as FPGA implementations.

Name	Description	Unit	Admissible Values
Model Type	Selects the type of implementation (inside CPU or FPGA)	N/A	{CPU, FPGA}
Number of Valves	Number of valves simulated by the block	N/A	integers {1,2,3,.... , 12}
Intercalate Ports	Changes the way how the electrical ports in the block are showed. This can simplify the connection to external elements in the circuit. When this option is unchecked, the positive terminals of the valves are placed on the left side of the block and the negative terminals on the right side (i.e. left side → +1,+2,+3,... ; right side → -1,-2,-3,... ). When the option is checked, one positive terminal is intercalated with one negative terminal (i.e. left side → +1,-2,+3,... ; right side → -1,+2,-3,... )	N/A	[Checked / Unchecked]
External snubber	This parameter allows to change the type of snubber used on each valve. When this parameter is checked the block implements an external RC snubber in parallel to each valve. When unchecked, the RC snubber is implemented in parallel to the diodes of the valve equivalent model. In both cases the snubber parameters are selected in the block mask parameters Rs and Cs. In case of external snubber, the parallel resistance to Cs is set internally to have a time constant of 4 ms (this time constant could be changed upon request).	N/A	[Checked / Unchecked]
Snubber resistance Rs [Ohm]	Sets the snubber resistance value	Ohms	>=0
Snubber capacitance Cs [Farads]	Sets the snubber capacitance value	Farads	>=0

CPU Model Parameters

The following table presents the block parameters that are available when the CPU implementation is selected

Name	Description	Unit	Admissible Values
CPU Model Type	Selects the type of model to be used in the CPU: Average Model (AVM) or Switched Function Model (SFM)	N/A	{AVM, SFM}
Base value for total Vcap [Volts]	Sets the nominal voltage of the valves. This means the maximum voltage that a valve can generate when all the SMs are in insertion mode and have a capacitor voltage equal to 1 p.u.	Volts	>=0
Initial SM capacitor voltage Vcap [Volts]	Sets the initial voltage value on each SM capacitor. For starting the simulation with 1 p.u. this value should be equal to the Base value for total Vcap parameter divided by the total number of SMs in each valve.	Volts	>=0
Sample time [seconds]	Sample time step used for discrete calculation	Seconds	>=0
Number of capacitors per valve	Specifies the number of capacitors for each valve. In case of Half-Bridge and Full-Bridge sub-modules, this number is equal to the number of sub-modules per valve. For sub-modules with two capacitors (CD-SM for example) this parameter should be twice the number of sub-modules.	N/A	>=0
SM switch forward voltage Vf [Volts]	Equivalent forward voltage in the ON-state for each semiconductor switch on each SM	Volts	>=0
SM switch ON-state resistance Ron [Ohms]	Equivalent ON-state resistance for each semiconductor switch on each SM	Ohms	>=0

FPGA Model Parameters

The following table presents the block parameters that are available when the FPGA implementation is selected

Name	Description	Unit	Admissible Values
OpCntrl / OpLnk block	Specifies the OpCntrl or OpLnk block to be used to connect the FPGA with the CPU model. The data of the MMCValves block will be exchanged with he FPGA specified by the selected OpCntrl /OpLnk block. To set this parameter the user should use one of the possible options in the list. The list is updated according to the OpCntrl or OpLnk blocks available in the same computation subsystem of the MMCValves block. If there are no OpCntrl/OpLnk blocks in the same computation subsystem, the block will give an error/warning message to the user. The model can be still compiled but the block will be not connected to the FPGA so the model will not behave as expected.	N/A	The list is updated according to the available OpCntrl / OpLnk blocks in the model
FPGA Control / Link Name	hows the name used in the selected OpCntrl or OpLnk block. The parameter cannot be set manually, it is updated automatically when selecting a OpCntrl / OpLnk block from the list on the OpCntrl / OpLnk block parameter.	N/A	string
Maximum number of SMs per valve in FPGA license	This parameter must match the available number of SMs supported in the FPGA license	N/A	integers
Valve group ID	Specifies in which logical group inside the FPGA the valves are simulated.	N/A	Depending on FPGA firmware : integers {0,1} or integers {2,3}

Inputs

Name

Description

Unit

Admissible Values

MMCPara

It is a bus signal that contains the parameters set coming from the MMC Valves Parameters Block block

N/A

ValveCtrl

Contains the control signals for the valves. This signal is generated by the MMC Valves Low Level Control Block block. According to the type of model the signal has different formatting and contents. In the following, the formatting of the ValveCtrl input is explained.

CPU implementation

Average Model

For an Average model in CPU, ValveCtrl is a bus signal containing the following signals:

v1, v2, v3, .... → each of this signals is a bus containing the modulation index for each valve. The signal v1 contains the modulation index for valve 1, the signal v2 the modulation index for valve 2 and so on. The ValveCtrl input must contain as much signals as the number of valves selected in the Number of Valves parameter. For example, if the number of valves is three only v1, v2 and v3 are required but if is 12 then the block expects 12 signals : v1, v2, v3 .... v12. The modulation index for each valve should be in the range of [ 0 , 1 ] if the valve only contains unipolar SMs (Half Bridge for example) or in the range of [ -1 , 1 ] if the valve has bipolar SMs (Full-bridge for example). Going beyond these ranges could result in unexpected behavior.

Switched function model

For a switched function model implemented in the CPU, ValveCtrl is a bus signal containing the following signals:

v1, v2, v3, .... → each of this signals is a bus containing the control signals for all the SMs in each valve. The signal v1 contains the controls signals for valve 1, the signal v2 the control signals for valve 2 and so on. The ValveCtrl input must contain as much signals as the number of valves selected in the Number of Valves parameter. For example, if the number of valves is three only v1, v2 and v3 are required but if is 12 then the block expects 12 signals : v1, v2, v3 .... v12.

Each of these signals (v1, v2, v3, ... ) is also a bus containing the following signals:

g1, g2, g3, g4, g5 → each signal is a vector containing the gate signals for each SM switch. The number of elements in the g1 to g5 vectors must match the number of SMs in the valve. The position in the vector indicates the SM, for example the first element on g1 refers to the control signal of the switch g1 of the first SM, while the 13th element on g4 refers to the control signal of the switch g4 on the 13th SM. For each signal, 1 means the corresponding switch is closed while 0 means that it is open. The SMs are counted from the positive terminal of the valve to the negative terminal, i.e. the first SM being the closest to the positive terminal. Note that each valve control signal (v1, v2, v3, ... ) expects always the five signals g1 to g5, even if the SM does not have all the switches (for example a Half-Bridge SM only has g1 and g2). Thus for sub-modules with less than 5 switches, a zero can be sent to the not needed gating signals.

FPGA implementation

In the case of a model implementation on the FPGA, the ValveCtrl is an empty signal since the control signals are sent to the model inside the FPGA.

Binary if switched function model, or in p.u. if average model.

[-1,1] if average model or { 0, 1} if switched function model.

Outputs

Name

Description

Unit

Admissible Values

meas

It is a bus signal that contains the measurements on each of the valves. The signals are organized as follows:

Ival → It is a vector containing the current on the valves. The position on the vector indicates the corresponding valve, i.e. the first element corresponds to the valve number 1, the second to the valve 2 and so on. The current direction is positive when flowing from the positive terminal (indicated by a '+' on the block) to the negative terminal (indicated by a '-' on the block).
v_vlv → It is a vector containing the voltage at the terminals of each valve. The position on the vector indicates the corresponding valve, i.e. the first element corresponds to the valve number 1, the second to the valve 2 and so on. The voltage is measured from the negative to the positive terminal on each valve.
Vs → is a bus signal containing the following signals :
- Vsp → is a vector containing the voltage on the internal equivalent voltage source on each valve for positive current direction. The position on the vector indicates the corresponding valve.
- Vsn → is a vector containing the voltage on the internal equivalent voltage source on each valve for negative current direction. The position on the vector indicates the corresponding valve.

[A], [V]

(-inf, inf)

Vcap

It is a bus signal that contains the valves capacitor voltages. The signals in the bus are:

Vcap → This signal contains all the SM capacitor voltages. It is available only for a switched function model implementation in the CPU. The signal is organized as a bus containing:
- Vc1,Vc2,Vc3, ... Vc12 → Each of this signals is a vector that contains the SM capacitor voltages of each valve. The signal Vc1 contains the capacitor voltages for valve 1, the signal Vc2 the capacitor voltages for valve 2 and so on. The size of each of these signals is equal to the number of SMs per valve. The position in the vector indicates the SM in the valve, being the first one the SM closest to the positive terminal.
Vcapave→ This signal contains the average value of all the SM capacitor voltages on each valve, i.e. ΣVcap / Nsm. This measurement is only available for the CPU model implementations (switched function or average model), for FPGA implementation it is given by the MMC Valves Low Level Control Block block. In case of average model, this measurement represents the voltage on the equivalent capacitor on the valve. The Vcapave output is organized as a vector, the number of elements depends on the number of valves and the position in the vector represents the corresponding valve, i.e. the first element corresponds to the valve number 1, the second to the valve 2 and so on.

in p.u.

[0,inf)

Electrical ports

Name	Description
+1, +2,+3 ,.... +12	These ports correspond to the positive terminal of the valves. The number indicates the corresponding valve.
-1, -2,-3 ,.... -12	These ports correspond to the negative terminal of the valves. The number indicates the corresponding valve.

Examples

HVDC Point-to-Point Link with two MMCs: In this example see how to use the MMCValves block together with MMC Valves Parameters Block and MMC Valves Low Level Control Block blocks. To implement a monopolar HVDC link with two MMCs
HVDC Bipole Point-to-Point MMC link:In this example see how a Bipole Point-to-Point HVDC link is implemented with four MMCs.
STATCOM: In this example see how to use the MMC Valves block with only three valves of Full Bridge type in an STATCOM application.
Multiterminal MMC HVDC Grid: In this example learn how to use several MMC Valves block in the same simulation to simulate large MMC based power systems.
Matrix Modular Multilevel Converter (M3C): In this example you can find a simulation of an AC-AC matrix converter using nine valves in the same MMC Valves block

Limitations

The number of valves per MMCValves block is limited to 12. Though, several MMCValves blocks could be used in the same system for larger applications. However the number of valves per FPGA is limited to 12 in the current firmware versions.
All the valves inside the block have the same characteristics, like number of SMs, type of SM, snubber, switch resistance, and SM capacitance. In the FPGA implementation however, some discrepancy can be set between the different SMs in terms of SM capacitance and discharge resistance (see MMC Valves Parameters Block Block for more details). To simulate converters with different type of valves, several MMCValves blocks can be used together in the same simulation.
Each valve can simulate only one type of SMs in the switched function model on CPU. For FPGA implementation, three different kind of SMs can be set for the same valve (see MMC Valves Parameters Block Block for more details). For average model it is not recommended to run MMC with mixed SMs in the current version.
The type of model cannot be changed on-line during simulation. The simulation must be stopped and the model must be recompiled each time the type of model changes.

Version History

This block has been introduced in MMC 2.10.0

MMC User Documentation

MMCValves Block

Description

Mask and Parameters

General Parameters

CPU Model Parameters

FPGA Model Parameters

Inputs

Outputs

Electrical ports

Examples

Limitations

Version History

See Also